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| 型號： | ADUC831BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START |
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REV. 0
–36–
ADuC831
PWM MODES OF OPERATION
MODE 0: PWM Disabled
The PWM is disabled, allowing P2.6 and P2.7 to be used as
normal.
MODE 1: Single Variable Resolution PWM
In Mode 1, both the pulse length and the cycle time (period) are
programmable in user code, allowing the resolution of the PWM
to be variable.
PWM1H/L sets the period of the output waveform. Reducing
PWM1H/L reduces the resolution of the PWM output but
increases the maximum output rate of the PWM.
(For example, setting PWM1H/L to 65536 gives a 16-bit PWM
with a maximum output rate of 244 Hz (16 MHz/65536). Setting
PWM1H/L to 4096 gives a 12-bit PWM with a maximum output
rate of 3906 Hz (16 MHz/4096).)
PWM0H/L sets the duty cycle of the PWM output waveform, as
shown in the diagram below.
P2.7
PWM COUNTER
PWM1H/L
0
PWM0H/L
Figure 27. ADuC831 PWM in Mode 1
MODE 2: Twin 8-Bit PWM
In Mode 2, the duty cycle of the PWM outputs and the resolution
of the PWM outputs are both programmable. The maximum
resolution of the PWM output is eight bits.
PWM1L sets the period for both PWM outputs. Typically, this
will be set to 255 (FFH) to give an 8-bit PWM, although it is
possible to reduce this as necessary. A value of 100 could be
loaded here to give a percentage PWM (i.e., the PWM is
accurate to 1%).
The outputs of the PWM at P2.6 and P2.7 are shown in the
diagram below. As can be seen, the output of PWM0 (P2.6) goes
low when the PWM counter equals PWM0L. The output of
PWM1 (P2.7) goes high when the PWM counter equals PWM1H,
and goes low again when the PWM counter equals PWM0H.
Setting PWM1H to 0 ensures that both PWM outputs start
simultaneously.
P2.7
P2.6
PWM COUNTER
PWM1H
0
PWM1L
PWM0H
PWM0L
Figure 28. PWM Mode 2
MODE 3: Twin 16-Bit PWM
In Mode 3, the PWM counter is fixed to count from 0 to 65536
giving a fixed 16-bit PWM. Operating from the 16 MHz core clock
results in a PWM output rate of 244 Hz. The duty cycle of the
PWM outputs at P2.6 and P2.7 are independently programmable.
As shown in Figure 29, while the PWM counter is less than
PWM0H/L, the output of PWM0 (P2.6) is high. Once the PWM
counter equals PWM0H/L, then PWM0 (P2.6) goes low and
remains low until the PWM counter rolls over.
Similarly while the PWM counter is less than PWM1H/L, the
output of PWM1 (P2.7) is high. Once the PWM counter equals
PWM1H/L, then PWM1 (P2.7) goes low and remains low until
the PWM counter rolls over.
In this mode, both PWM outputs are synchronized. Once the
PWM counter rolls over to 0, both PWM0 (P2.6) and PWM1
(P2.7) will go high.
P2.7
P2.6
PWM COUNTER
PWM1H/L
0
65536
PWM0H/L
Figure 29. PWM Mode 3
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