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| 型號： | ADUC831BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 76/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC831QSZ-ND - KIT DEV FOR ADUC831 QUICK START |
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REV. 0
ADuC831
–9–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Type
Function
DVDD
PDigital Positive Supply Voltage, 3 V or 5 V Nominal
AVDD
PAnalog Positive Supply Voltage, 3 V or 5 V Nominal
CREF
IDecoupling Input for On-Chip Reference. Connect 0.1
F between this pin and AGND.
VREF
I/O
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this
appears at the pin. This pin can be overdriven by an external reference.
AGND
G
Analog Ground. Ground reference point for the analog circuitry.
P1.0–P1.7
I
Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults to Analog Input mode, to configure
any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share
the following functionality.
ADC0–ADC7
I
Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
T2
I
Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a
1-to-0 transition of the T2 input.
T2EX
I
Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for
Counter 2.
SS
I
Slave Select Input for the SPI Interface
SDATA
I/O
User Selectable, I
2C Compatible or SPI Data Input/Output Pin
SCLOCK
I/O
Serial Clock Pin for I
2C Compatible or SPI Serial Interface Clock
MOSI
I/O
SPI Master Output/Slave Input Data I/O Pin for SPI Interface
MISO
I/O
SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface
DAC0
O
Voltage Output from DAC0
DAC1
O
Voltage Output from DAC1
RESET
I
Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device.
P3.0–P3.7
I/O
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, Port 3
pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins
also contain various secondary functions which are described below.
PWMC
I
PWM Clock Input
PWM0
O
PWM0 Voltage Output. PWM outputs can be configured to use ports 2.6 and 2.7, or 3.4 and 3.3.
PWM1
O
PWM1 Voltage Output. See CFG831 Register for further information.
RxD
I/O
Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port
TxD
O
Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port
INT0
I
Interrupt 0, programmable edge- or level-triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 0.
INT1
I
Interrupt 1, programmable edge- or level-triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 1.
T0
I
Timer/Counter 0 Input
T1
I
Timer/Counter 1 Input
CONVST
I
Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is Enabled.
A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion.
WR
OWrite Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
RD
ORead Control Signal, Logic Output. Enables the external data memory to Port 0.
XTAL2
O
Output of the Inverting Oscillator Amplifier
XTAL1
I
Input to the Inverting Oscillator Amplifier, and input to the internal clock generator circuits.
DGND
G
Digital Ground. Ground reference point for the digital circuitry.
P2.0–P2.7
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are
(A8–A15)
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, Port 2
(A16–A23)
pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits
the high order address bytes during fetches from external program memory and middle and high order
address bytes during accesses to the external 24-bit external data memory space.
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