參數(shù)資料
型號(hào)： ADUC848BSZ62-3
廠商： Analog Devices Inc
文件頁數(shù)： 45/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH W/16BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x16b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 41 of 108
ADCMODE (ADC MODE REGISTER)
Used to control the operational mode of both ADCs.
SFR Address:
D1H
Power-On Default:
08H
Bit Addressable:
No
Table 24. ADCMODE SFR Bit Designations
Bit No.
Name
Description
7
–––
Not Implemented. Write Don’t Care.
6
REJ60
Automatic 60 Hz Notch Select Bit.
Setting this bit places a notch in the frequency response at 60 Hz, allowing simultaneous 50 Hz and 60 Hz
rejection at an SF word of 82 decimal. This 60 Hz notch can be set only if SF ≥68 decimal, that is, the regular
filter notch must be ≤60 Hz. This second notch is placed at 60 Hz only if the device clock is at 32.768 kHz.
5
ADC0EN
Primary ADC Enable.
Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0 below.
Cleared by the user to place the primary ADC into power-down mode.
4
ADC1EN
(ADuC845 only)
Auxiliary (ADuC845 only) ADC Enable.
Set by the user to enable the auxiliary (ADuC845 only) ADC and place it in the mode selected in MD2–MD0
below.
Cleared by the user to place the auxiliary (ADuC845 only) ADC in power-down mode.
3
CHOP
Chop Mode Disable.
Set by the user to disable chop mode on both the primary and auxiliary (ADuC845 only) ADC allowing a
three times higher ADC data throughput. SF values as low as 3 are allowed with this bit set, giving up to
1.3 kHz ADC update rates.
Cleared by the user to enable chop mode on both the primary and auxiliary (ADuC845 only) ADC.
2, 1, 0
MD2, MD1, MD0
Primary and Auxiliary (ADuC845 only) ADC Mode Bits.
These bits select the operational mode of the enabled ADC as follows:
MD2
MD1
MD0
0
ADC Power-Down Mode (Power-On Default).
0
1
Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state
although the modulator clocks are still provided.
0
1
0
Single Conversion Mode. In single conversion mode, a single conversion is performed
on the enabled ADC. Upon completion of a conversion, the ADC data registers
(ADC0H/M/L and/or ADC1H/M/L (ADuC845 only)) are updated. The relevant flags in
the ADCSTAT SFR are written, and power-down is re-entered with the MD2MD0
accordingly being written to 000.
Note that ADC0L is not available on the ADuC848.
0
1
Continuous Conversion. In continuous conversion mode, the ADC data registers are
regularly updated at the selected update rate (see the Sinc Filter SFR Bit Designations
1
0
Internal Zero-Scale Calibration. Internal short automatically connected to the
enabled ADC input(s).
1
0
1
Internal Full-Scale Calibration. Internal or external REFIN± or REFIN2± VREF (as
determined by XREF bits in ADC0CON2 and/or AXREF (ADuC845 only) in ADC1CON
(ADuC845 only) is automatically connected to the enabled ADC input(s) for this
calibration.
1
0
System Zero-Scale Calibration. User should connect system zero-scale input to the
enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the
ADC0CON2 and ADC1CON (ADuC845 only) registers.
1
System Full-Scale Calibration. User should connect system full-scale input to the
enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the
ADC0CON2 and ADC1CON (ADuC845 only) registers.
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