參數(shù)資料
型號： ADUC848BSZ62-3
廠商： Analog Devices Inc
文件頁數(shù)： 82/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH W/16BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x16b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 75 of 108
TIMERS/COUNTERS
The ADuC845/ADuC847/ADuC848 have three 16-bit timer/
counters: Timer 0, Timer 1, and Timer 2. The timer/counter
hardware is included on-chip to relieve the processor core of the
overhead inherent in implementing timer/counter functionality
in software. Each timer/counter consists of two 8-bit registers:
THx and TLx (x = 0, 1, or 2). All three can be configured to
operate either as timers or as event counters.
When functioning as a timer, the TLx register is incremented
every machine cycle. Thus, one can think of it as counting
machine cycles. Because a machine cycle on a single-cycle core
consists of one core clock period, the maximum count rate is
the core clock frequency.
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a
1-to-0 transition, the maximum count rate is half the core clock
frequency.
There are no restrictions on the duty cycle of the external input
signal, but, to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via three SFRs:
TMOD, TCON—Control and Configuration for Timers 0 and 1.
T2CON—Control and Configuration for Timer 2.
TMOD—Timer/Counter 0 and 1 Mode Register
SFR Address:
89H
Power-On Default:
00H
Bit Addressable:
No
Table 50. TMOD SFR Bit Designation
Bit No.
Name
Description
7
Gate
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is set.
Cleared by software to enable Timer 1 whenever the TR1control bit is set.
6
C/T
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select the timer operation (input from internal system clock).
5, 4
M1, M0
Timer 1 Mode Select Bits.
M1
M0
Description
0
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it
overflows.
1
Timer/Counter 1 Stopped.
3
Gate
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set.
Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
2
C/T
Timer 0 Timer or Counter Select Bit.
Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
1, 0
M1, M0
Timer 0 Mode Select Bits.
M1
M0
Description
0
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it
overflows.
1
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
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