The power supply monitor, once enabled, monitors the " />
參數(shù)資料
型號(hào)： ADUC848BSZ62-3
廠商： Analog Devices Inc
文件頁數(shù)： 74/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH W/16BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x16b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 68 of 108
POWER SUPPLY MONITOR
The power supply monitor, once enabled, monitors the DVDD
and AVDD supplies on the parts. It indicates when any of the
supply pins drop below one of four user-selectable voltage trip
points from 2.63 V to 4.63 V. For correct operation of the power
supply monitor function, AVDD must be equal to or greater than
2.63 V. Monitor function is controlled via the PSMCON SFR. If
enabled via the IEIP2 SFR, the monitor interrupts the core by
using the PSMI bit in the PSMCON SFR. This bit is not cleared
until the failing power supply returns above the trip point for at
least 250 ms.
The monitor function allows the user to save working registers
to avoid possible data loss due to the low supply condition, and
also ensures that normal code execution does not resume until a
safe supply level is well established. The supply monitor is also
protected against spurious glitches triggering the interrupt
circuit.
The 5 V part has an internal POR trip level of 4.63 V, which
means that there are no usable DVDD PSM trip levels on the 5 V
part. The 3 V part has a POR trip level of 2.63 V following a
reset and initialization sequence, allowing all relevant PSM trip
points to be used.
PSMCON—Power Supply Monitor Control Register
SFR Address:
DFH
Power-On Default:
DEH
Bit Addressable:
No
Table 43. PSMCON SFR Bit Designations
Bit No.
Name
Description
7
CMPD
DVDD Comparator Bit.
This read-only bit directly reflects the state of the DVDD comparator.
Read 1 indicates that the DVDD supply is above its selected trip point.
Read 0 indicates that the DVDD supply is below its selected trip point.
6
CMPA
AVDD Comparator Bit.
This read-only bit directly reflects the state of the AVDD comparator.
Read 1 indicates that the AVDD supply is above its selected trip point.
Read 0 indicates that the AVDD supply is below its selected trip point.
5
PSMI
Power Supply Monitor Interrupt Bit.
Set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The PSMI
bit can be used to interrupt the processor. Once CMPD and/or CMPA returns (and remains) high, a 250 ms
counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the
user. However, if either comparator output is low, it is not possible for the user to clear PSMI.
4, 3
TPD1, TPD0
DVDD Trip Point Selection Bits.
A 5 V part has no valid PSM trip points. If the DVDD supply falls below the 4.63 V point, the part resets (POR). For a
3 V part, all relevant PSM trip points are valid. The 3 V POR trip point is 2.63 V (fixed).
These bits select the DVDD trip point voltage as follows:
TPD1
TPD0
Selected DVDD Trip Point (V)
0
4.63
0
1
3.08
1
0
2.93
1
2.63
2, 1
TPA1, TPA0
AVDD Trip Point Selection Bits. These bits select the AVDD trip point voltage as follows:
TPA1
TPA0
Selected AVDD Trip Point (V)
0
4.63
0
1
3.08
1
0
2.93
1
2.63
0
PSMEN
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
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