參數(shù)資料
型號(hào)： ADV601
廠商： Analog Devices, Inc.
元件分類： 視頻Codec
英文描述： Low Cost Multiformat Video Codec
中文描述： 低成本多格式視頻解碼器
文件頁(yè)數(shù)： 37/52頁(yè)
文件大?。?/td> 606K
代理商： ADV601
ADV601
–37–
REV. 0
TIMING PARAMETERS
This section contains signal timing information for the ADV601. Timing descriptions for the following items appear in this
section:
Clock signal timing
Video data transfer timing (CCIR-656, Gray Scale/Philips, and Multiplexed Philips formats)
Host data transfer timing (direct register read/write access)
DSP data transfer (serial data transfer)
Clock Signal Timing
The diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin
loading of 50 pF.
Table XX. Video Clock Period, Frequency, Drift and Jitter
Min VCLK_CYC
Period
Nominal VCLK_CYC
Period (Frequency)
Max VCLK_CYC
Period
1, 2
Video Format
CCIR-601 PAL
Square Pixel PAL
CCIR-601 NTSC
Square Pixel NTSC
35.2 ns
32.2 ns
35.2 ns
38.7 ns
37 ns (27 MHz)
33.89 ns (29.5 MHz)
37 ns (27 MHz)
40.75 ns (24.54 MHz)
38.9 ns
35.5 ns
38.9 ns
42.7 ns
NOTES
1
VCLK Period Drift =
±
0.1 (VCLK_CYC/field.
2
VCLK edge-to-edge jitter = 1 ns.
Table XXI. Video Clock Duty Cycle
Min
Nominal
Max
VCLK Duty Cycle
1
(40%)
(50%)
(60%)
NOTE
1
VCLK Duty Cyle = t
VCLK_HI
/(t
VCLK_LO
)
×
100.
Table XXII. Video Clock Timing Parameters
Parameter
Description
Min
Max
Unit
t
VCLK_CYC
t
VCLKO_D0
t
VCLKO_D1
VCLK Signal, Cycle Time (1/Frequency) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz
(See Video Clock Period Table)
10
10
29
29
ns
ns
TEST CONDITIONS
Figure 23 shows test condition voltage reference and device
loading information. These test conditions consider an output
as
disabled
when the output stops driving and goes from the
measured high or low voltage to a high impedance state. Tests
measure output disable time (t
DISABLE
) as the time between the
reference input signal crossing +1.5 V and the time that the
output reaches the high impedance state (also +1.5 V). Simi-
larly, these tests conditions consider an output as
enabled
when
the output leaves the high impedance state and begins driving a
measured high or low voltage. Tests measure output enable time
(t
ENABLE
) as the time between the reference input signal crossing
+1.5 V and the time that the output reaches the measured high
or low voltage.
INPUT
REFERENCE
SIGNAL
OUTPUT
SIGNAL
t
DISABLED
t
ENABLED
1.5V
V
OH
V
OL
V
IH
V
IL
1.5V
INPUT & OUTPUT VOLTAGE/TIMING REFERENCES
DEVICE LOADING FOR AC MEASUREMENTS
TO
OUTPIN
2pF
+1.5V
I
OL
I
OH
Figure 23. Test Condition Voltage Reference and Device Loading
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