參數(shù)資料
型號(hào)： ADV601
廠商： Analog Devices, Inc.
元件分類： 視頻Codec
英文描述： Low Cost Multiformat Video Codec
中文描述： 低成本多格式視頻解碼器
文件頁數(shù)： 47/52頁
文件大小： 606K
代理商： ADV601
ADV601
–47–
REV. 0
Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV601’s Compressed Data register. Ac-
cesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt
Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address
,
Indirect
Regis
ter Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the
RD
or
WR
signal assertion timing, your system does
NOT
have to wait for the
ACK
signal between new compressed data addresses.
Table XXXV. Host (Compressed Data) Read Timing Parameters
Parameter
Description
Min
Max
Unit
t
RD_CD_RDC
t
RD_CD_PWA
t
RD_CD_PWD
t
ADR_CD_RDS
t
ADR_CD_RDH
t
DATA_CD_RDD
t
DATA_CD_RDOH
t
ACK_CD_RDD
t
ACK_CD_RDOH
RD
Signal, Compressed Data Direct Register, Read Cycle Time
RD
Signal, Compressed Data Direct Register, Pulse Width Asserted
RD
Signal, Compressed Data Direct Register, Pulse Width Deasserted
ADR Bus, Compressed Data Direct Register, Read Setup
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
DATA Bus, Compressed Data Direct Register, Read Delay
DATA Bus, Compressed Data Direct Register, Read Output Hold
ACK
Signal, Compressed Data Direct Register, Read Delay
ACK
Signal, Compressed Data Direct Register, Read Output Hold
28
10
10
2
2
N/A
18
N/A
9
N/A
N/A
N/A
N/A
N/A
10
N/A
18
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
(I) ADR,
BE
,
CS
(I)
RD
(O) DATA
(O)
ACK
VALID
VALID
VALID
VALID
t
ADR_CD_RDS
t
DATA_CD_RDD
t
ACK_CD_RDD
t
ACK_CD_RDOH
t
DATA_CD_RDOH
t
ADR_CD_RDH
t
RD_CD_RDC
t
RD_CD_PWA
t
RD_CD_PWD
Figure 39. Host (Compressed Data) Read Transfer Timing
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