參數(shù)資料
型號(hào)： ADV601
廠商： Analog Devices, Inc.
元件分類： 視頻Codec
英文描述： Low Cost Multiformat Video Codec
中文描述： 低成本多格式視頻解碼器
文件頁(yè)數(shù)： 38/52頁(yè)
文件大?。?/td> 606K
代理商： ADV601
ADV601
–38–
REV. 0
CCIR-656 Video Format Timing
The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal), and frame (vertical) data in CCIR-656 video
mode. All output values assume a maximum pin loading of 50 pF. Note that in timing diagrams for CCIR-656 video, the label
CTRL
indicates the VSYNC, HSYNC, and FIELD pins. Also note that for CCIR-656 video mode, the CREF pin is unused.
Table XXIII. CCIR-656 Video—Decode Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Units
t
VDATA_DC_D
t
VDATA_DC_OH
t
CTRL_DC_D
t
CTRL_DC_OH
VDATA Signals, Decode CCIR656 Mode, Delay
VDATA Signals, Decode CCIR656 Mode, Output Hold
CTRL Signals, Decode CCIR656 Mode, Delay
CTRL Signals, Decode CCIR656 Mode, Output Hold
N/A
2
N/A
3
14
N/A
11
N/A
ns
ns
ns
ns
(O) CTRL
(O) VCLKO
t
CTRL_DC_OH
(O) VDATA
t
VDATA_DC_OH
t
VDATA_DC_D
VALID
VALID
VALID
t
CTRL_DC_D
VALID
VALID
VALID
Figure 25. CCIR-656 Video—Decode Pixel (YCrCb) Transfer Timing
Table XXIV. CCIR-656 Video—Encode Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Units
t
VDATA_EC_S
t
VDATA_EC_H
t
CTRL_EC_D
t
CTRL_EC_OH
VDATA Bus, Encode CCIR656 Mode, Setup
VDATA Bus, Encode CCIR656 Mode, Hold
CTRL Signals, Encode CCIR656 Mode, Delay
CTRL Signals, Encode CCIR656 Mode, Output Hold
2
5
N/A
20
N/A
N/A
33
N/A
ns
ns
ns
ns
t
VDATA_EC_H
(O) CTRL
(I) VCLK
(I) VDATA
ASSERTED
VALID
ASSERTED
VALID
t
VDATA_EC_S
t
CTRL_EC_D
t
CTRL_EC_OH
Figure 26. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Timing
(I) VCLK
(O) VCLKO
(VCLK2 = 0)
(I) VCLKO
(VCLK2 = 1)
t
VCLK_CYC
t
VCLKO_D0
t
VCLKO_D1
NOTE:
USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS.
DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE.
Figure 24. Video Clock Timing
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