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參數(shù)資料
| 型號： | ADV7120KSTZ30-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO 3CH 30MHZ 48-LQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 2,000 |
| 設置時間： | 12ns |
| 位數(shù)： | 8 |
| 數(shù)據接口： | 并聯(lián) |
| 轉換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 625mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 3 電流，單極 |
| 采樣率（每秒）： | 30M |
ADV7120
REV. B
–7–
If we, therefore, have a graphics system with a 1024
× 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
Dot Rate = 1024
× 1024 × 60/0.8
= 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7120
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV7120 be driven by a TTL buffer (e.g.,
74F244).
92.5 IRE
7.5 IRE
40 IRE
WHITE LEVEL
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
19.05
0.714
26.67
1.000
1.44
0.054
9.05
0.340
0
7.62
0.286
0
mA
V
mA
V
RED, BLUE
GREEN
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75
LOAD.
2. V
REF = 1.235V, RSET = 560, ISYNC CONNECTED TO IOG.
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform
Video Synchronization and Control
The ADV7120 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
The ISYNC current output is typically connected directly to the
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV7120’s analog outputs, the SYNC in-
put should be tied to logic low and the ISYNC should be con-
nected to analog ground.
Reference Input
An external 1.23 V voltage reference is required to drive
the ADV7120. The AD589 from Analog Devices is an
ideal choice of reference. It is a two-terminal, low cost,
temperature compensated bandgap voltage reference which
provides a fixed 1.23 V output voltage for input currents
between 50
A and 5 mA. Figure 4 shows a typical refer-
ence circuit connection diagram. The voltage reference gets
its current drive from the ADV7120’s VAA through an on-
board 1 k
resistor to the V
REF pin. A 0.1
F ceramic ca-
pacitor is required between the COMP pin and VAA.
This is necessary so as to provide compensation for the
internal reference amplifier.
Table I. Video Output Truth Table
IOG
IOR, IOB
REF
DAC
Description
(mA)
l
(mA)
WHITE
SYNC
BLANK
Input Data
WHITE LEVEL
26.67
19.05
1
xxH
WHITE LEVEL
26.67
19.05
0
1
FFH
VIDEO
video + 9.05
video + 1.44
0
1
data
VIDEO to BLANK
video + 1.44
0
1
data
BLACK LEVEL
9.05
1.44
0
1
00H
BLACK to BLANK
1.44
0
1
00H
BLANK LEVEL
7.62
0
1
0
xxH
SYNC LEVEL
0
xxH
NOTE
Typical with full-scale IOG = 26.67 mA.
VREF = 1.235 V, RSET = 560 , ISYNC connected to IOG.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| ADV7120KSTZ50 | 功能描述:IC DAC VIDEO 3-CH 50MHZ 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| ADV7121 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 80 MHz, Triple 10-Bit Video DACs |
| ADV7121JN30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC without Color Palette |
| ADV7121JN50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC without Color Palette |
| ADV7121JN80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC without Color Palette |
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