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參數(shù)資料
| 型號(hào)： | ADV7120KSTZ30-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO 3CH 30MHZ 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 設(shè)置時(shí)間： | 12ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 625mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 3 電流，單極 |
| 采樣率（每秒）： | 30M |
ADV7120
REV. B
–5–
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog out-
puts, IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK.
While BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are
ignored.
SYNC
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE
current source on the ISYNC output. SYNC does not override any other control or data input; therefore, it
should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.
CLOCK
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC,
BLANK
and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated TTL buffer.
REF WHITE
Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB
outputs to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7). REF WHITE is
latched on the rising edge of clock.
R0–R7,
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.
G0–G7,
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
B0–B7
regular PCB power or ground plane.
IOR, IOG, IOB
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving
a doubly terminated 75
coaxial cable. All three current outputs should have similar output loads whether
or not they are all being used.
ISYNC
Sync current output. This high impedance current source can be directly connected to the IOG output. This
allows sync information to be encoded onto the green channel. ISYNC does not output any current while
SYNC
is at logical zero. The amount of current output at ISYNC while SYNC is at logical one is given by:
ISYNC (mA) = 3,455
× V
REF (V)/ RSET (
)
If sync information is not required on the green channel, ISYNC should be connected to AGND.
FS ADJUST
Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of
the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current.
The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to
IOG) is given by:
RSET (
) = 12,082
× V
REF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR and IOB is given by:
IOR, IOB (mA) = 8,628
× V
REF (V)/ RSET (
)
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1
F ceramic capaci-
tor must be connected between COMP and VAA.
VREF
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an ex-
ternal resistor divider network is not recommended. A 0.1
F decoupling ceramic capacitor should be con-
nected between VREF and VAA.
VAA
Analog power supply (5 V
± 5%). All V
AA pins on the ADV7120 must be connected.
GND
Ground. All GND pins must be connected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7120KSTZ50 | 功能描述:IC DAC VIDEO 3-CH 50MHZ 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| ADV7121 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 80 MHz, Triple 10-Bit Video DACs |
| ADV7121JN30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC without Color Palette |
| ADV7121JN50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC without Color Palette |
| ADV7121JN80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC without Color Palette |
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