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參數(shù)資料
| 型號(hào)： | ADV7180BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 33/116頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SDTV 40-LFCSP |
| 設(shè)計(jì)資源： | Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 數(shù)碼相機(jī)，手機(jī)，便攜式視頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADV7180LQEBZ-ND - BOARD EVALUATION ADV7180 EVAL-ADV7180LFEBZ-ND - BOARD EVAL FOR ADV7180 LFCSP |
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Data Sheet
ADV7180
Rev. I | Page 23 of 116
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVING MODES
Power-Down
PDBP, Address 0x0F[2]
The digital supply of the ADV7180 can be shut down by using
the PWRDWN pin or via I2C1 (see the PWRDWN, Address
pin has the higher priority. The default is to give the pin
(PWRDWN) priority2. This allows the user to have the
ADV7180 powered down by default at power-up without the
need for an I2C write.
When PDBP is 0 (default), the digital supply power is controlled
by the PWRDWN pin2 (the PWRDWN bit, Address 0x0F[5], is
disregarded).
When PDBP is 1, the PWRDWN bit has priority (the pin is
disregarded).
PWRDWN, Address 0x0F[5]
When PDBP is set to 1, setting the PWRDWN bit switches the
ADV7180 to a chip-wide power-down mode. The power-down
stops the clock from entering the digital section of the chip,
thereby freezing its operation. No I2C bits are lost during power-
down. The PWRDWN bit also affects the analog blocks and
switches them into low current modes. The I2C interface is
unaffected and remains operational in power-down mode.
The ADV7180 leaves the power-down state if the PWRDWN bit is
PDBP must be set to 1 for the PWRDWN bit to power down
the ADV7180.
When PWRDWN is 0 (default), the chip is operational. When
PWRDWN is 1, the ADV7180 is in a chip-wide power-down mode.
RESET CONTROL
Reset, Chip Reset, Address 0x0F[7]
Setting this bit, which is equivalent to controlling the RESET pin
to their default/power-up values. Note that some register bits do
not have a reset value specified. They keep their last written value.
Those bits are marked as having a reset value of x in the register
tables (see Table 107 and Table 108). After the reset sequence,
the part immediately starts to acquire the incoming video signal.
1
For 32-lead, I2C is the only power-down option.
2
For 64-lead, 48-lead, and 40-lead only.
After setting the reset bit (or initiating a reset via the RESET pin),
the part returns to the default for its primary mode of operation.
All I2C bits are loaded with their default values, making this bit
self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I2C writes are
performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented (see
the MPU Port Description section).
When the reset bit is 0 (default), operation is normal.
When the reset bit is 1, the reset sequence starts.
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03[6]
This bit allows the user to three-state the output drivers of the
Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the 48-lead,
40-lead, and 32-lead devices), HS, VS, FIELD (VS/FIELD pin for
the 48-lead, 40-lead, and 32-lead LFCSP), and SFL pins are
three-stated.
The timing pins (HS, VS, FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, see
Enable sections.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x1D[7]
This bit allows the output drivers for the LLC pin of the
ADV7180 to be three-stated. For more information on three-
state control, refer to the Three-State Output Drivers and the
Timing Signals Output Enable sections.
Individual drive strength controls are provided via the
DR_STR_x bits.
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
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