參數(shù)資料
型號: ADV7180BCPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 47/116頁
文件大?。?/td> 0K
描述: IC VIDEO DECODER SDTV 40-LFCSP
設(shè)計(jì)資源: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標(biāo)準(zhǔn)包裝: 2,500
類型: 視頻解碼器
應(yīng)用: 數(shù)碼相機(jī),手機(jī),便攜式視頻
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 帶卷 (TR)
配用: EVAL-ADV7180LQEBZ-ND - BOARD EVALUATION ADV7180
EVAL-ADV7180LFEBZ-ND - BOARD EVAL FOR ADV7180 LFCSP
ADV7180
Data Sheet
Rev. I | Page 36 of 116
CSFM[2:0], C Shaping Filter Mode, Address 0x17[7:5]
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see Setting 000
and Setting 001 in Table 37).
Table 37. CSFM Function
CSFM[2:0]
Description
000 (default)
Autoselection 1.5 MHz bandwidth
001
Autoselection 2.17 MHz bandwidth
010
SH1
011
SH2
100
SH3
101
SH4
110
SH5
111
Wideband mode
Figure 28 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (shown in red).
GAIN OPERATION
The gain control within the ADV7180 is done on a purely
digital basis. The input ADC supports a 10-bit range mapped
into a 1.0 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
As shown in Figure 30, the ADV7180 can decode a video signal
as long as it fits into the ADC window. The components for this
are the amplitude of the input signal and the dc level it resides on.
The dc level is set by the clamping circuitry (see the Clamp
Operation section).
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
Figure 29 shows a typical voltage divider network that is required
to keep the input video signal within the allowed range of the
ADC, 0 V to 1 V. Place this circuit before all analog inputs to
39
Ω
36
Ω
100nF
ANALOG VIDEO
INPUT
AIN_OF_ADV7180
05700-
024
Figure 29. Input Voltage Divider Network
The minimum supported amplitude of the input video is
determined by the ability of the ADV7180 to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
The possible AGC modes are shown in Table 38.
Table 38. AGC Modes
Input
Video Type
Luma Gain
Chroma Gain
Any
Manual gain luma
Manual gain chroma
CVBS
Dependent on
horizontal sync depth
Dependent on color-burst
amplitude taken from
luma path
Peak white
Dependent on color-burst
amplitude taken from
luma path
Y/C
Dependent on
horizontal sync depth
Dependent on color-burst
amplitude taken from
luma path
Peak white
Dependent on color-burst
amplitude
YPrPb
Dependent on
horizontal sync depth
Taken from luma path
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating and the AGC determined gain
at the time of the freeze to stay active until the loop is either
unfrozen or the gain mode of operation is changed.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1V RANGE FOR ADV7180)
DATA PRE-
PROCESSOR
(DPP)
ADC
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
MAXIMUM
VOLTAGE
MINIMUM
VOLTAGE
CLAMP
LEVEL
GAIN
CONTROL
05700-
025
Figure 30. Gain Control Overview
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