參數(shù)資料
型號(hào)： ADV7180BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 23/116頁
文件大小： 0K
描述： IC VIDEO DECODER SDTV 40-LFCSP
設(shè)計(jì)資源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
產(chǎn)品目錄頁面： 788 (CN2011-ZH PDF)
配用： EVAL-ADV7180LQEBZ-ND - BOARD EVALUATION ADV7180
EVAL-ADV7180LFEBZ-ND - BOARD EVAL FOR ADV7180 LFCSP
ADV7180
Data Sheet
Rev. I | Page 14 of 116
40-LEAD LFCSP
PIN 1
INDICATOR
1
DVDDIO
2
SFL
3
DGND
4
DVDDIO
5
P7
6
P6
7
P5
8
P4
9
P3
10
P2
23
AIN1
24
AGND
25
VREFP
26
VREFN
27
AVDD
28
AGND
29
AIN2
30
AIN3
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
22
TEST_0
21
AGND
1
L
C
1
2
X
T
A
L
1
3
X
T
A
L
1
5
D
G
N
D
1
7
P
0
1
6
P
1
8
P
W
R
D
W
N
1
9
E
L
P
F
2
0
P
V
D
1
4
D
V
D
3
S
D
A
T
A
3
4
S
C
L
K
3
5
D
G
N
D
3
6
D
V
D
3
7
V
S
/F
IE
L
D
3
8
IN
T
R
Q
3
9
H
S
4
0
D
G
N
D
3
2
A
L
S
B
3
1
R
E
S
E
T
LFCSP
TOP VIEW
(Not to Scale)
ADV7180
05
70
0-
00
7
Figure 9. 40-Lead LFCSP Pin Configuration
Table 10. 40-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1, 4
DVDDIO
P
Digital I/O Supply Voltage (1.8 V to 3.3 V).
2
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
3, 15, 35, 40
DGND
G
Ground for Digital Supply.
5 to 10, 16, 17
P7 to P2, P1, P0
O
Video Pixel Output Port.
11
LLC
O
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or
down according to video line length.
12
XTAL1
O
This pin should be connected to the 28.6363 MHz crystal or not connected if an external 1.8 V,
28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal
must be a fundamental crystal.
13
XTAL
I
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
14, 36
DVDD
P
Digital Supply Voltage (1.8 V).
18
PWRDWN
I
A logic low on this pin places the ADV7180 into power-down mode.
19
ELPF
I
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 57.
20
PVDD
P
PLL Supply Voltage (1.8 V).
21, 24, 28
AGND
G
Ground for Analog Supply.
22
TEST_0
I
This pin must be tied to DGND.
23, 29, 30
AIN1 to AIN3
I
Analog Video Input Channels.
25
VREFP
O
Internal Voltage Reference Output. See Figure 57 for recommended output circuitry.
26
VREFN
O
Internal Voltage Reference Output. See Figure 57 for recommended output circuitry.
27
AVDD
P
Analog Supply Voltage (1.8 V).
31
RESET
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7180 circuitry.
32
ALSB
I
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.
33
SDATA
I/O
I2C Port Serial Data Input/Output Pin.
34
SCLK
I
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
37
VS/FIELD
O
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
38
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
39
HS
O
Horizontal Synchronization Output Signal.
EPAD (EP)
The exposed pad must be connected to GND.
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ADV7180BCPZ 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40
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