參數(shù)資料
型號(hào)： ADV7180BSTZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 34/116頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO DECODER SDTV 64-LQFP
產(chǎn)品變化通告： ADV7180 Metal Mask Edit 22/Oct/2009
設(shè)計(jì)資源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 視頻解碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 788 (CN2011-ZH PDF)
配用： EVAL-ADV7180LQEBZ-ND - BOARD EVALUATION ADV7180
EVAL-ADV7180LFEBZ-ND - BOARD EVAL FOR ADV7180 LFCSP
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ADV7180
Data Sheet
Rev. I | Page 24 of 116
Timing Signals Output Enable
TIM_OE, Address 0x04[3]
The TIM_OE bit is regarded as an addition to the TOD bit. Setting
it high forces the output drivers for HS, VS, and FIELD into the
active state (that is, driving state) even if the TOD bit is set. If
TIM_OE is set to low, the HS, VS, and FIELD pins are three-
stated depending on the TOD bit. This functionality is beneficial if
the decoder is only used as a timing generator. This may be the
case if only the timing signals are extracted from an incoming
signal or if the part is in free-run mode, where a separate chip
can output a company logo, for example.
For more information on three-state control, see the Three-State
Individual drive strength controls are provided via the
DR_STR_x bits.
When TIM_OE is 0 (default), HS, VS, and FIELD are three-
stated according to the TOD bit.
When TIM_OE is 1, HS, VS, and FIELD are forced active all
the time.
Drive Strength Selection (Data)
DR_STR[1:0], Address 0xF4[5:4]
For EMC and crosstalk reasons, it may be desirable to strengthen or
weaken the drive strength of the output drivers. The DR_STR[1:0]
bits affect the P[15:0] for the 64-lead device or P[7:0] for the
48-lead, 40-lead, and 32-lead devices output drivers.
Note that DR_STR[1:0] also affects the drive strength of the
INTRQ interrupt pin on all ADV7180 models.
For more information on three-state control, see the Drive
(Sync) sections.
Table 16. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×)
01 (default)
Medium low drive strength (2×)
10
Medium high drive strength (3×)
11
High drive strength (4×)
Drive Strength Selection (Clock)
DR_STR_C[1:0], Address 0xF4[3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
Table 17. DR_STR_C Function
DR_STR_C[1:0]
Description
00
Low drive strength (1×)
01 (default)
Medium low drive strength (2×)
10
Medium high drive strength (3×)
11
High drive strength (4×)
Drive Strength Selection (Sync)
DR_STR_S[1:0], Address 0xF4[1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and FIELD are
driven. For more information, see the Drive Strength Selection
(Data) section.
Table 18. DR_STR_S Function
DR_STR_S[1:0]
Description
00
Low drive strength (1×)
01 (default)
Medium low drive strength (2×)
10
Medium high drive strength (3×)
11
High drive strength (4×)
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN, Address 0x04[1]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as genlock) from the ADV7180 core
to an encoder in a decoder/encoder back-to-back arrangement.
When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.
When EN_SFL_PIN is 1, the subcarrier frequency lock information
is presented on the SFL pin.
Polarity LLC Pin
PCLK, Address 0x37[0]
The polarity of the clock that leaves the ADV7180 via the LLC
pin can be inverted using the PCLK bit.
Changing the polarity of the LLC clock output may be necessary to
meet the setup-and-hold time expectations of follow-on chips.
When PCLK is 0, the LLC output polarity is inverted.
When PCLK is 1 (default), the LLC output polarity is normal
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7180BSTZ 制造商:Analog Devices 功能描述:Video IC
ADV7180BSTZ-REEL 功能描述:IC VIDEO DECODER SDTV 64-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類(lèi)型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤(pán) 包裝:帶卷 (TR) 其它名稱(chēng):296-32523-2TPS65198RUYT-ND
ADV7180KCP32Z 功能描述:IC VIDEO DECODER 10BIT 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話(huà)，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064
ADV7180KCP32Z-RL 功能描述:IC VIDEO DECODER 10BIT 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話(huà)，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064
ADV7180KST48Z 功能描述:IC VID DECOD SDTV 10BIT 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類(lèi)型:調(diào)諧器 應(yīng)用:移動(dòng)電話(huà)，手機(jī)，視頻顯示器 安裝類(lèi)型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱(chēng):SP000365064
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