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參數(shù)資料
| 型號： | AGL10002-FGG256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 13/204頁 |
| 文件大小： | 2800K |
| 代理商： | AGL10002-FGG256 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
1-5
VersaTiles
The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS core tiles. The IGLOO
VersaTile supports the following:
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-4 for VersaTile configurations.
For more information about VersaTiles, refer to the "VersaTile" section on page 2-2.
User Nonvolatile FlashROM
Actel IGLOO devices have 1 kbit of on-chip, user-
accessible, nonvolatile FlashROM. The FlashROM can be
used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example,
set-top boxes)
Secure key storage for secure communications
algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOO IEEE
1532 JTAG programming interface. The core can be
individually programmed (erased and written), and on-
chip AES decryption can be used selectively to securely
load data over public networks (except in the AGL030
device), as in security keys stored in the FlashROM for a
user design.
The FlashROM can be programmed via the JTAG
programming interface, and its contents can be read
back either through the JTAG programming interface or
via direct FPGA core addressing. Note that the FlashROM
can only be programmed from the JTAG interface and
cannot be programmed from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits;
however, reading is performed on a byte-by-byte basis
using a synchronous interface. A 7-bit address from the
FPGA core defines which of the 8 banks and which of the
16 bytes within that bank are being read. The three most
significant
bits
(MSBs)
of
the
FlashROM
address
determine the bank, and the four least significant bits
(LSBs) of the FlashROM address define the byte.
The Actel IGLOO development software solutions,
Libero
Integrated
Design
Environment
(IDE)
and
Designer, have extensive support for the FlashROM. One
such
feature
is
auto-generation
of
sequential
programming files for applications requiring a unique
serial number in each part. Another feature allows the
inclusion of static data for system version control. Data
for the FlashROM can be generated quickly and easily
using Actel Libero IDE and Designer software tools.
Comprehensive
programming
file
support
is
also
included to allow for easy programming of large
numbers of parts with differing FlashROM contents.
SRAM and FIFO
IGLOO
devices
(except
the
AGL030
device)
have
embedded SRAM blocks along their north and south
sides. Each variable-aspect-ratio SRAM block is 4,608 bits
in size. Available memory configurations are 256×18,
512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks
have independent read and write ports that can be
configured with different bit widths on each port. For
example, data can be sent through a 4-bit port and read
as a single bitstream. The embedded SRAM blocks can be
initialized via the device JTAG port (ROM emulation
mode) using the UJTAG macro (except in the AGL030
device).
Figure 1-4 VersaTile Configurations
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10002-FGG484I | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10002-FGG484 | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10005-FFG144I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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