參數(shù)資料
型號(hào)： AGL10002-FGG256
元件分類： FPGA
英文描述： FPGA, 1000000 GATES, 200 MHz, PBGA144
封裝： 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144
文件頁(yè)數(shù)： 159/204頁(yè)
文件大?。?/td> 2800K
代理商： AGL10002-FGG256
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 44
Advanced v0.1
5 V Output Tolerance
IGLOO I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS
mode to reliably drive 5 V TTL receivers. It is also critical
that there be NO external I/O pull-up resistor to 5 V, since
this resistor would pull the I/O pad voltage beyond the
3.6 V absolute maximum value and consequently cause
damage to the I/O.
When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, IGLOO
I/Os can directly drive signals into 5 V TTL receivers. In
fact, VOL =0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and
3.3 V LVCMOS modes exceeds the VIL =0.8 V and
VIH = 2 V level requirements of 5 V TTL receivers.
Therefore, level 1 and level 0 will be recognized correctly
by 5 V TTL receivers.
Simultaneous Switching Outputs (SSOs)
and Printed Circuit Board Layout
SSOs can cause signal integrity problems on adjacent
signals that are not part of the SSO bus. Both inductive
and capacitive coupling parasitics of bond wires inside
packages and of traces on PCBs will transfer noise from
SSO busses onto signals adjacent to those busses.
Additionally, SSOs can produce ground bounce noise and
VCCI dip noise. These two noise types are caused by
rapidly changing currents through GND and VCCI
package pin inductances during switching activities
Ground bounce noise voltage = L(GND) × di/dt
EQ 2-1
VCCI dip noise voltage = L(VCCI) × di/dt
EQ 2-2
Any group of four or more input pins switching on the
same clock edge is considered an SSO bus. The shielding
should be done both on the board and inside the
package unless otherwise described.
In-package shielding can be achieved in several ways; the
required shielding will vary depending on whether pins
next
to
the
SSO
bus
are
LVTTL/LVCMOS
inputs,
LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL
inputs and outputs. Board traces in the vicinity of the
SSO bus have to be adequately shielded from mutual
coupling and inductive noise that can be generated by
the SSO bus. Also, noise generated by the SSO bus needs
to be reduced inside the package.
PCBs perform an important function in feeding stable
supply voltages to the IC and, at the same time,
maintaining signal integrity between devices.
Key issues that need to considered are as follows:
Power and ground plane design and decoupling
network design
Transmission line reflections and terminations
相關(guān)PDF資料
PDF描述
AGL10002-FGG484I FPGA, 1000000 GATES, 200 MHz, PBGA484
AGL10002-FGG484 FPGA, 1000000 GATES, 200 MHz, PBGA484
AGL10005-FFG144I FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFG144 FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFG256I FPGA, 1000000 GATES, 250 MHz, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGL1000V2-CS144 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS281 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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