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參數(shù)資料
| 型號： | AGL10002-FGG256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 140/204頁 |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10002-FGG256 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 26
Advanced v0.1
Signal Descriptions for RAM4K94
The following signals are used to configure the RAM4K9
memory element:
WIDTHA and WIDTHB
These signals enable the RAM to be configured in one of
four allowable aspect ratios (Table 2-6).
BLKA and BLKB
These signals are active low and will enable the
respective ports when asserted. When a BLKx signal is
deasserted, that port’s outputs hold the previous value.
WENA and WENB
These signals switch the RAM between read and write
modes for the respective ports. A LOW on these signals
indicates a write operation, and a HIGH indicates a read.
CLKA and CLKB
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
PIPEA and PIPEB
These signals are used to specify pipelined read on the
output.
A
LOW
on
PIPEA
or
PIPEB
indicates
a
nonpipelined read, and the data appears on the
corresponding output in the same clock cycle. A HIGH
indicates a pipelined read, and data appears on the
corresponding output in the next clock cycle.
WMODEA and WMODEB
These signals are used to configure the behavior of the
output when the RAM is in write mode. A LOW on these
signals makes the output retain data from the previous
read. A HIGH indicates pass-through behavior, wherein
the data being written will appear immediately on the
output. This signal is overridden when the RAM is being
read.
RESET
This active low signal resets the control logic, forces the
output hold state registers to zero, disables reads and
writes from the SRAM block, and clears the data hold
registers when asserted. It does not reset the contents of
the memory array.
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous reset
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning with Table 3-147 on page 3-93 for the
specifications.
ADDRA and ADDRB
These are used as read or write addresses, and they are 12
bits wide. When a depth of less than 4 k is specified, the
unused high-order bits must be grounded (Table 2-7).
DINA and DINB
These are the input data signals, and they are nine bits
wide. Not all nine bits are valid in all configurations.
When a data width less than nine is specified, unused
high-order signals must be grounded (Table 2-8).
DOUTA and DOUTB
These are the nine-bit output data signals. Not all nine
bits are valid in all configurations. As with DINA and
DINB, high-order bits may not be used (Table 2-8). The
output data on unused pins is undefined.
4. The AGL030 device does not support SRAM or FIFO.
Table 2-6 Allowable Aspect Ratio Settings for
WIDTHA[1:0]
WIDTHA[1:0]
WIDTHB[1:0]
D×W
00
4k×1
01
2k×2
10
1k×4
11
512×9
Note: The aspect ratio settings are constant and cannot be
changed on the fly.
Table 2-7 Address Pins Unused/Used for Various
Supported Bus Widths
D×W
ADDRx
Unused
Used
4k×1
None
[11:0]
2k×2
[11]
[10:0]
1k×4
[11:10]
[9:0]
512×9
[11:9]
[8:0]
Note: The "x" in ADDRx implies A or B.
Table 2-8 Unused/Used Input and Output Data Pins for
Various Supported Bus Widths
D×W
DINx/DOUTx
Unused
Used
4k×1
[8:1]
[0]
2k×2
[8:2]
[1:0]
1k×4
[8:4]
[3:0]
512×9
None
[8:0]
Note: The "x" in DINx or DOUTx implies A or B.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10002-FGG484I | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10002-FGG484 | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10005-FFG144I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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