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| 型號： | AGL10005-FFG256I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, FBGA-144 |
| 文件頁數(shù)： | 141/204頁 |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FFG256I |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
2-27
Signal Descriptions for RAM512X185
RAM512X18
has
slightly
different
behavior
than
RAM4K9, as it has dedicated read and write ports.
WW and RW
These signals enable the RAM to be configured in one of
the two allowable aspect ratios (Table 2-9).
WD and RD
These are the input and output data signals, and they
are 18 bits wide. When a 512×9 aspect ratio is used for
write, WD[17:9] are unused and must be grounded. If
this aspect ratio is used for read, RD[17:9] are undefined.
WADDR and RADDR
These are read and write addresses, and they are nine
bits wide. When the 256×18 aspect ratio is used for write
or read, WADDR[8] or RADDR[8] are unused and must be
grounded.
WCLK and RCLK
These signals are the write and read clocks, respectively.
They can be clocked on the rising or falling edge of
WCLK and RCLK.
WEN and REN
These
signals
are
the
write
and
read
enables,
respectively. They are both active low by default. These
signals can be configured as active high.
RESET
This active low signal resets the control logic, forces the
output hold state registers to zero, disables reads and
writes from the SRAM block, and clears the data hold
registers when asserted. It does not reset the contents of
the memory array.
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous reset
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning with Table 3-148 on page 3-94 for the
specifications.
PIPE
This signal is used to specify pipelined read on the
output. A LOW on PIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A HIGH indicates a pipelined read, and data
appears on the output in the next clock cycle.
Clocking
The dual-port SRAM blocks are only clocked on the rising
edge. SmartGen allows falling-edge-triggered clocks by
adding inverters to the netlist, hence achieving dual-port
SRAM blocks that are clocked on either edge (rising or
falling). For dual-port SRAM, each port can be clocked on
either edge and/or by separate clocks by port.
IGLOO devices support inversion (bubble pushing)
throughout the FPGA architecture, including the clock
input to the SRAM modules. Inversions added to the
SRAM clock pin on the design schematic or in the HDL
code will be automatically accounted for during design
compile without incurring additional delay in the clock
path.
The two-port SRAM can be clocked on the rising or
falling edge of WCLK and RCLK.
If negative-edge RAM and FIFO clocking is selected for
memory macros, clock edge inversion management
(bubble pushing) is automatically used within the IGLOO
development tools, without performance penalty.
Modes of Operation
There are two read modes and one write mode:
Read Nonpipelined (synchronous—1 clock edge):
In the standard read mode, new data is driven
onto the RD bus in the same clock cycle following
RA and REN valid. The read address is registered
on the read port clock active edge, and data
appears at RD after the RAM access time. Setting
PIPE to OFF enables this mode.
Read Pipelined (synchronous—2 clock edges): The
pipelined mode incurs an additional clock delay
from address to data but enables operation at a
much higher frequency. The read address is
registered on the read port active clock edge, and
the read data is registered and appears at RD after
the second read clock edge. Setting PIPE to ON
enables this mode.
Write (synchronous—1 clock edge): On the write
clock active edge, the write data is written into
the SRAM at the write address when WEN is HIGH.
The setup times of the write address, write
enables, and write data are minimal with respect
to the write clock. Write and read transfers are
described with timing requirements in the "DDR
5. The AGL030 device does not support SRAM or FIFO.
Table 2-9 Aspect Ratio Settings for WW[1:0]
WW[1:0]
RW[1:0]
D×W
01
512×9
10
256×18
00, 11
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FFG256 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFG484I | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FFG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FFGG144I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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