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參數(shù)資料
| 型號(hào)： | AGL10005-FFGG144 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁(yè)數(shù)： | 177/204頁(yè) |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FFGG144 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 60
Advanced v0.1
JTAG Pins
IGLOO devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). VCC must also be powered for
the JTAG state machine to operate, even if the device is
in bypass mode; VJTAG alone is insufficient. Both VJTAG
and VCC to the IGLOO part must be supplied to allow
JTAG signals to transition the IGLOO device. Isolating the
JTAG power supply in a separate I/O bank gives greater
flexibility in supply selection and simplifies power supply
and PCB design. If the JTAG interface is neither used nor
planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG.
The TCK pin does not have an internal pull-up/-down
resistor. If JTAG is not used, Actel recommends tying off
TCK to GND through a resistor placed close to the FPGA
pin. This prevents JTAG operation in case TMS enters an
undesired state.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements. Refer to Table 2-33 for
more information.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG
usage. There is an internal weak pull-up resistor on the
TDI pin.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG
usage.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1532 boundary
scan pins (TCK, TDI, TDO, TRST). There is an internal weak
pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to
asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the
TRST pin. If JTAG is not used, an external pull-down
resistor could be included to ensure the test access port
(TAP) is held in reset mode. The resistor values must be
chosen from Table 2-33 and must satisfy the parallel
resistance value requirement. The values in Table 2-33
correspond to the resistor recommended when a single
device is used and the equivalent parallel resistor when
multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could
allow entrance to an undesired JTAG state. In such cases,
Actel recommends tying off TRST to GND through a
resistor placed close to the FPGA pin.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements.
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the
PCB. These pins should be left unconnected.
Table 2-33 Recommended Tie-Off Values for the TCK and
TRST Pins
VJTAG
Tie-Off Resistance
VJTAG at 3.3 V
200
Ω to 1 kΩ
VJTAG at 2.5 V
200
Ω to 1 kΩ
VJTAG at 1.8 V
500
Ω to 1 kΩ
VJTAG at 1.5 V
500
Ω to 1 kΩ
Notes:
1. Equivalent parallel resistance if more than one device is on
the JTAG chain.
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled down.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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