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參數(shù)資料
| 型號(hào)： | AGL10005-FFGG144 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁(yè)數(shù)： | 183/204頁(yè) |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FFGG144 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
1- 2
A dvanced v0. 1
security allow for secure, remote field updates over
public networks such as the Internet, and ensure that
valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. The contents
of a programmed IGLOO device cannot be read back,
although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent
component of the IGLOO family. The flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. The IGLOO family,
with FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible.
An
IGLOO
device
provides
the
most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information
in
on-chip
flash
cells.
Once
programmed,
the
configuration data is an inherent part of the FPGA
structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based
FPGAs). Therefore, flash-based IGLOO FPGAs do not
require
system
configuration
components
such
as
EEPROMs
or
microcontrollers
to
load
device
configuration data. This reduces bill-of-materials costs
and PCB area, and increases security and system
reliability.
Live at Power-Up
The Actel flash-based IGLOO devices support Level 0 of
the LAPU classification standard. This feature helps in
system component initialization, execution of critical
tasks before the processor wakes up, setup and
configuration of memory blocks, clock generation, and
bus activity management. The LAPU feature of flash-
based IGLOO devices greatly simplifies total system
design and reduces total system cost, often eliminating
the need for CPLDs and clock generation PLLs that are
used for these purposes in a system. In addition, glitches
and brownouts in system power will not corrupt the
IGLOO device's flash configuration, and unlike SRAM-
based FPGAs, the device will not have to be reloaded
when system power is restored. This enables the
reduction or complete removal of the configuration
PROM, expensive voltage monitor, brownout detection,
and clock generator devices from the PCB design. Flash-
based IGLOO devices simplify total system design and
reduce cost and design risk while increasing system
reliability and improving system initialization time.
IGLOO flash FPGAs allow the user to quickly enter and
exit Flash*Freeze mode. This is done almost instantly
(within 1 s) and the device retains configuration and
data in registers and RAM. Unlike SRAM-based FPGAs
the device does not need to reload configuration and
design state from external memory components; instead
it retains all necessary information to resume operation
immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
performance, and ease of use. Unlike SRAM-based
FPGAs, Flash-based IGLOO devices allow all functionality
to be live at power-up; no external boot PROM is
required. On-board security mechanisms prevent access
to all the programming information and enable secure
remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to
support future design iterations and field upgrades with
confidence that valuable intellectual property cannot be
compromised or copied. Secure ISP can be performed
using the industry-standard AES algorithm. The IGLOO
family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the IGLOO
family
a
cost-effective
ASIC
replacement
solution,
especially
for
applications
in
the
consumer,
networking/communications, computing, and avionics
markets.
Refer to the "I/O Power-Up and Supply Voltage
Industrial)" section on page 3-4 for more information.
Firm Errors
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of IGLOO flash-
based FPGAs. Once it is programmed, the flash cell
configuration element of IGLOO FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily
be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO family offers many benefits, including
nonvolatility
and
reprogrammability
through
an
advanced flash-based, 130-nm LVCMOS process with
seven layers of metal. Standard CMOS design techniques
are used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant flash switches allows
for very high logic utilization without compromising
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FFGG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG256 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG484I | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FFGG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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