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參數(shù)資料
| 型號(hào)： | AGL10005-FFGG144 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁(yè)數(shù)： | 180/204頁(yè) |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FFGG144 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
2-63
JTAG 1532
IGLOO devices support the JTAG-based IEEE 1532
standard for ISP. In order to start JTAG operations the
IGLOO device should exit Flash*Freeze mode and be in
normal operation for before starting to send JTAG
commands to the device. As part of this support, when a
IGLOO device is in an unprogrammed state, all user I/O
pins are disabled. This is achieved by keeping the global
IO_EN signal deactivated, which also has the effect of
disabling the input buffers. The SAMPLE/PRELOAD
instruction captures the status of pads in parallel and
shifts them out as new data is shifted in for loading into
the Boundary Scan Register. When the IGLOO device is in
an
unprogrammed
state,
the
SAMPLE/PRELOAD
instruction has no effect on I/O status; however, it will
continue to shift in new data to be loaded into the BSR.
Therefore, when SAMPLE/PRELOAD is used on an
unprogrammed device, the BSR will be loaded with
undefined data.
For JTAG timing information on setup, hold, and fall
times, refer to the FlashPro User’s Guide.
Boundary Scan
IGLOO devices are compatible with IEEE Standard 1149.1,
which defines a hardware architecture and the set of
mechanisms for boundary scan testing. JTAG operations
are used during boundary scan testing; therefore, the
Flash*Freeze pin must be deasserted for successful
boundary scan operations. The basic IGLOO boundary
scan logic circuit is composed of the TAP controller, test
data registers, and instruction register (Figure 2-45 on
page 2-65). This circuit supports all mandatory IEEE
1149.1 instructions (EXTEST, SAMPLE/PRELOAD, and
BYPASS) and the optional IDCODE instruction (Table 2-
34).
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, TDO (test
data input and output), TMS (test mode selector), and
TRST (test reset input). TMS, TDI, and TRST are equipped
with pull-up resistors to ensure proper operation when
no input data is supplied to them. These pins are
dedicated for boundary scan test usage. Refer to the
"JTAG Pins" section on page 2-60 for pull-up/down
recommendations for TDO and TCK pins. Table 2-35 gives
pull-down recommendations for the TRST and TCK
pins.
Table 2-34 Boundary Scan Opcodes
Hex Opcode
EXTEST
00
HIGHZ
07
USERCODE
0E
SAMPLE/PRELOAD
01
IDCODE
0F
CLAMP
05
BYPASS
FF
Table 2-35 TRST and TCK Pull-Down Recommendations
VJTAG
Tie-Off Resistance*
VJTAG at 3.3 V
200
Ω to 1 kΩ
VJTAG at 2.5 V
200
Ω to 1 kΩ
VJTAG at 1.8 V
500
Ω to 1 kΩ
VJTAG at 1.5 V
500
Ω to 1 kΩ
Note: *Equivalent parallel resistance if more than one device
is on JTAG chain (Figure 2-43)
Note: TCK is correctly wired with an equivalent tie-off resistance
of 500
Ω, which satisfies the table for V
JTAG of 1.5 V. The
resistor values for TRST are not appropriate in this case, as
the tie-off resistance of 375
Ω is below the recommended
minimum for VJTAG = 1.5 V, but would be appropriate for a
VJTAG setting of 2.5 V or 3.3 V.
Figure 2-43 Parallel Resistance on JTAG Chain of Devices
TDI
TDO
JTAG
Header
Actel
FPGA 1
Actel
FPGA 2
Actel
FPGA 3
Actel
FPGA 4
2 k
Ω
2 k
Ω
2 k
Ω
2 k
Ω
1.5 V
TCK
TRST
VJTAG
GND
1.5 k
Ω
1.5 k
Ω
1.5 k
Ω
1.5 k
Ω
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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