參數(shù)資料
型號(hào)： AGL10005-FGG484
元件分類： FPGA
英文描述： FPGA, 1000000 GATES, 250 MHz, PBGA484
封裝： 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144
文件頁(yè)數(shù)： 166/204頁(yè)
文件大?。?/td> 2800K
代理商： AGL10005-FGG484
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 50
Advanced v0.1
Flash*Freeze Technology and
Low-Power Modes
The
Actel
IGLOO
family
offers
ultra-low
power
consumption in Active and Static modes by utilizing the
unique Flash*Freeze technology.
IGLOO devices offer various power-saving modes that
enable every system to utilize modes that achieve the
lowest total system power.
Low-Power Active capability (static idle) allows for ultra-
low power consumption (from 25 W) while the IGLOO
device is operational in the system by maintaining SRAM,
registers, I/Os, and logic functions.
Flash*Freeze technology provides an ultra-low-power
static mode (Flash*Freeze mode) that retains all SRAM
and register information with rapid recovery to Active
(operating) mode. The mechanism enables the user to
quickly (within 1 s) enter and exit Flash*Freeze mode by
activating the Flash*Freeze (FF) pin while all power
supplies are kept in their original states. In addition, I/Os
and clocks connected to the FPGA can still be driven or
toggling without impact on device power consumption.
While in Flash*Freeze mode, the device retains all core
register states and SRAM information. No power is
consumed by the I/O banks, clocks, JTAG pins, or PLLs,
and the IGLOO device consumes as little as 5 W in this
mode.
Power Conservation Techniques
IGLOO FPGAs provide many ways to conserve power;
however, there are also many design techniques that can
be
used
to
reduce
power
on
the
board.
Actel
recommends that the user tie any unused power supplies
(such as VCCPLL, VCCI, VMV, and VPUMP) and unused I/O
signals to the ground plane.
Using low-voltage CMOS I/O standard signals and the
lowest drive strength will reduce switching and result
with lower power consumption in Active mode.
Low-Power Modes Overview
Table 2-27 summarizes the IGLOO low-power modes that
achieve power consumption reduction when the FPGA or
system is idle.
Table 2-27 IGLOO Power Modes Summary
Mode
VCCI
VCC
Core
Clocks
ULSICC
Macro
To Enter
Mode
To Resume
Operation
Trigger
Active
On
N/A
Initiate clock
None
–
Static
Idle
On
Off
N/A
Stop clock
Initiate clock
External
Flash*Freeze
type 1
On
On
N/A
Assert FF pin
Deassert FF
pin
External
Flash*Freeze
type 2
On
On
Used to
enter
Flash*Freeze
mode
Assert FF pin
and assert
LSICC
Deassert FF
pin
External
Sleep
On
Off
N/A
Shut down
VCC
Turn on VCC
supply
External
Shutdown
Off
N/A
Shut down
VCC and VCCI
supplies
Turn on VCC
and VCCI
supplies
External
Note: External clocks can be left toggling when while the device is in Flash*Freeze mode. Clocks generated by the embedded PLL will be
turned off automatically.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGL1000V2-CS144 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS281 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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