2-30 Revision 23 Table 2-32 Summary of I/O Timing Characteristics鈥擲oftware Default Settings, Std. S" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGL400V5-FG256
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 192/250闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 400K 256FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 9216
RAM 浣嶇附瑷�(j矛)锛� 55296
杓稿叆/杓稿嚭鏁�(sh霉)锛� 178
闁€(m茅n)鏁�(sh霉)锛� 400000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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IGLOO DC and Switching Characteristics
2-30
Revision 23
Table 2-32 Summary of I/O Timing Characteristics鈥擲oftware Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per
standard)
Applicable to Standard Plus I/O Banks
I/O
S
tan
dard
Dr
ive
S
trength
Eq
uivalen
tSo
ft
ware
Default
Drive
S
trength
Option
1
(mA
)
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
esi
st
or
(
)
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZLS
(ns)
t ZH
S
(ns)
Unit
s
3.3 V
LVTTL /
3.3 V
LVCMOS
12 mA
12
High
5
鈥�
0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99 ns
3.3 V
LVCMOS
Wide
Range2
100 A
12
High
5
鈥�
0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51 ns
2.5 V
LVCMOS
12 mA
12
High
5
鈥�
0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11 ns
1.8 V
LVCMOS
8 mA
8
High
5
鈥�
0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36 ns
1.5 V
LVCMOS
4 mA
4
High
5
鈥�
0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59 ns
3.3 V PCI
Per PCI
spec
鈥�
High
10
25 2 0.97 1.97 0.18 0.73 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns
3.3 V
PCI-X
Per PCI-
X spec
鈥�
High
10
25 2 0.97 1.97 0.19 0.70 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for
connectivity. This resistor is not required during normal operation.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
AGL400V5-FG256I 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.5V 256FPBGA RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�(j矛):221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€(m茅n)鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū(ch膿ng):220-1241
AGL400V5-FG484 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 484FBGA RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
AGL400V5-FG484I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 484FBGA RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€(m茅n)鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
AGL400V5-FGG144 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 144FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€(m茅n)鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
AGL400V5-FGG144I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 400K 144FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�