2-26 Revision 13 Table 2-26 Summary of I/O Timing Characteristics—Software Default Settings
參數(shù)資料
型號： AGLE3000V2-FGG896I
廠商： Microsemi SoC
文件頁數(shù)： 102/166頁
文件大小： 0K
描述： IC FPGA 1KB FLASH 3M 896-FBGA
標準包裝： 27
系列： IGLOOe
邏輯元件/單元數(shù)： 75264
RAM 位總計： 516096
輸入/輸出數(shù)： 620
門數(shù)： 3000000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 896-BGA
供應(yīng)商設(shè)備封裝： 896-FBGA（31x31）
IGLOOe DC and Switching Characteristics
2-26
Revision 13
Table 2-26 Summary of I/O Timing Characteristics—Software Default Settings
Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI (per standard)
I/O Standard
Drive
S
trength
(mA)
Eq
uivalen
tSo
ft
ware
De
fault
Drive
S
trength
Option
1 (mA)
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
esi
st
or
(
)
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t PYS
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZLS
(ns)
t ZH
S
(ns)
Unit
s
3.3 V LVTTL /
3.3 V LVCMOS
12
12 High 5
–
1.55 2.47 0.26 1.31 1.58 1.10 2.51 2.04 3.28 3.97 8.29 7.82 ns
3.3 V LVCMOS
Wide Range1,2
100 A 12 High 35
–
1.55 3.40 0.26 1.66 2.14 1.10 3.40 2.68 4.55 5.49 9.19 8.46 ns
2.5 V LVCMOS
12
12 High 5
–
1.55 2.51 0.26 1.55 1.77 1.10 2.54 2.22 3.36 3.85 8.33 8.00 ns
1.8 V LVCMOS
12
12 High 5
–
1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns
1.5 V LVCMOS
12
12 High 5
–
1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns
1.2 V LVCMOS
2
High 5
–
1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns
1.2 V LVCMOS
Wide Range1,3
100 A
2
High 5
–
1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns
3.3 V PCI
PerPCI
spec
–
High 10
254 1.55 2.76 0.26 1.19 1.63 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns
3.3 V PCI-X
Per
PCI-X
spec
–
High 10
254 1.55 2.76 0.25 1.22 1.58 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns
3.3 V GTL
205
–
High 10
25 1.55 2.08 0.25 2.76
–
1.10 2.09 2.08
–
7.88 7.87 ns
2.5 V GTL
205
–
High 10
25 1.55 2.17 0.25 2.35
–
1.10 2.20 2.13
–
7.99 7.91 ns
3.3 V GTL+
35
–
High 10
25 1.55 2.12 0.25 1.62
–
1.10 2.14 2.07
–
7.93 7.85 ns
2.5 V GTL+
33
–
High 10
25 1.55 2.25 0.25 1.55
–
1.10 2.27 2.10
–
8.06 7.89 ns
HSTL (I)
8
–
High 20
50 1.55 3.09 0.25 1.95
–
1.10 3.11 3.09
–
8.90 8.88 ns
HSTL (II)
15
–
High 20
25 1.55 2.94 0.25 1.95
–
1.10 2.98 2.74
–
8.77 8.53 ns
SSTL2 (I)
15
–
High 30
50 1.55 2.18 0.25 1.40
–
1.10 2.21 2.03
–
7.99 7.82 ns
SSTL2 (II)
18
–
High 30
25 1.55 2.21 0.25 1.40
–
1.10 2.24 1.97
–
8.03 7.76 ns
SSTL3 (I)
14
–
High 30
50 1.55 2.33 0.25 1.33
–
1.10 2.36 2.02
–
8.15 7.81 ns
SSTL3 (II)
21
–
High 30
25 1.55 2.13 0.25 1.33
–
1.10 2.16 1.89
–
7.94 7.67 ns
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-49 for
connectivity. This resistor is not required during normal operation.
5. Output drive strength is below JEDEC specification.
6. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
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