Revision 13 2-21 HSTL (II) 15 mA5 High –0.3 VREF – 0.1 VREF + 0.1 3.6 " />
參數(shù)資料
型號: AGLE3000V2-FGG896I
廠商: Microsemi SoC
文件頁數(shù): 96/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 3M 896-FBGA
標準包裝: 27
系列: IGLOOe
邏輯元件/單元數(shù): 75264
RAM 位總計: 516096
輸入/輸出數(shù): 620
門數(shù): 3000000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 896-BGA
供應(yīng)商設(shè)備封裝: 896-FBGA(31x31)
IGLOOe Low Power Flash FPGAs
Revision 13
2-21
HSTL (II)
15 mA5
High –0.3 VREF – 0.1
VREF + 0.1
3.6
0.4
VCCI – 0.4
15
SSTL2 (I)
15 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.54
VCCI – 0.62 15
15
SSTL2 (II)
18 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.35
VCCI – 0.43 18
18
SSTL3 (I)
14 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.7
VCCI – 1.1 14
14
SSTL3 (II)
21 mA
High –0.3 VREF – 0.2
VREF + 0.2
3.6
0.5
VCCI – 0.9 21
21
Table 2-21 Summary of Maximum and Minimum DC Input and Output Levels (continued)
Applicable to Commercial and Industrial Conditions
I/O
Standard
Drive
Strength
Equivalent
Software
Default
Drive
Strength2
Slew
Rate
VIL
VIH
VOL
VOH
IOL1 IOH1
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Notes:
1. Currents are measured at 85°C junction temperature.
2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification.
4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
5. Output drive strength is below JEDEC specification.
6. Output Slew Rates can be extracted from IBIS Models, http://www.microsemi.com/soc/download/ibis/default.aspx.
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