Revision 13 2-9 Power per I/O Pin Table 2-13 Summary of I/O Input Buffer Power (per pin) – Default I/O Softwa" />
參數(shù)資料
型號: AGLE3000V5-FGG896
廠商: Microsemi SoC
文件頁數(shù): 83/166頁
文件大小: 0K
描述: IC FPGA 1KB FLASH 3M 896-FBGA
標準包裝: 27
系列: IGLOOe
邏輯元件/單元數(shù): 75264
RAM 位總計: 516096
輸入/輸出數(shù): 620
門數(shù): 3000000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 896-BGA
供應(yīng)商設(shè)備封裝: 896-FBGA(31x31)
IGLOOe Low Power Flash FPGAs
Revision 13
2-9
Power per I/O Pin
Table 2-13 Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
VCCI
(V)
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (W/MHz)2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3
16.34
3.3 V LVTTL/LVCMOS – Schmitt trigger
3.3
24.49
3.3 V LVCMOS Wide Range 3
3.3
16.34
3.3 V LVCMOS Wide Range – Schmitt trigger 3
3.3
24.49
2.5 V LVCMOS
2.5
4.71
2.5 V LVCMOS
2.5
6.13
1.8 V LVCMOS
1.8
1.66
1.8 V LVCMOS – Schmitt trigger
1.8
1.78
1.5 V LVCMOS (JESD8-11)
1.5
1.01
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
1.5
0.97
1.2 V LVCMOS 4
1.2
0.60
1.2 V LVCMOS – Schmitt trigger 4
1.2
0.53
1.2 V LVCMOS Wide Range 4
1.2
0.60
1.2 V LVCMOS Wide Range – Schmitt trigger 4
1.2
0.53
3.3 V PCI
3.3
17.76
3.3 V PCI – Schmitt trigger
3.3
19.10
3.3 V PCI-X
3.3
17.76
3.3 V PCI-X – Schmitt trigger
3.3
19.10
Voltage-Referenced
3.3 V GTL
3.3
2.90
7.14
2.5 V GTL
2.5
2.13
3.54
3.3 V GTL+
3.3
2.81
2.91
2.5 V GTL+
2.5
2.57
2.61
HSTL (I)
1.5
0.17
0.79
HSTL (II)
1.5
0.17
.079
SSTL2 (I)
2.5
1.38
3.26
SSTL2 (II)
2.5
1.38
3.26
SSTL3 (I)
3.3
3.21
7.97
SSTL3 (II)
3.3
3.21
7.97
Differential
LVDS
2.5
2.26
0.89
LVPECL
3.3
5.71
1.94
Notes:
1. PDC6 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
4. Applicable for IGLOOe V2 devices only.
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