Revision 13 2-107 Applies to 1.2 V DC Core Voltage Table 2-150 FIFO Commercial-Case C" />
參數(shù)資料
型號: AGLE600V2-FGG484I
廠商: Microsemi SoC
文件頁數(shù): 26/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 600K 484-FBGA
標(biāo)準(zhǔn)包裝: 60
系列: IGLOOe
邏輯元件/單元數(shù): 13824
RAM 位總計: 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
IGLOOe Low Power Flash FPGAs
Revision 13
2-107
Applies to 1.2 V DC Core Voltage
Table 2-150 FIFO
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
tENS
REN, WEN Setup Time
4.13
ns
tENH
REN, WEN Hold Time
0.31
ns
tBKS
BLK Setup Time
0.47
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
1.56
ns
tDH
Input Data (WD) Hold Time
0.49
ns
tCKQ1
Clock HIGH to New Data Valid on RD (pass-through)
6.80
ns
tCKQ2
Clock HIGH to New Data Valid on RD (pipelined)
3.62
ns
tRCKEF
RCLK HIGH to Empty Flag Valid
7.23
ns
tWCKFF
WCLK HIGH to Full Flag Valid
6.85
ns
tCKAF
Clock HIGH to Almost Empty/Full Flag Valid
26.61
ns
tRSTFG
RESET LOW to Empty/Full Flag Valid
7.12
ns
tRSTAF
RESET LOW to Almost Empty/Full Flag Valid
26.33
ns
tRSTBQ
RESET LOW to Data Out LOW on RD (pass-through)
4.09
ns
RESET LOW to Data Out LOW on RD (pipelined)
4.09
ns
tREMRSTB
RESET Removal
1.23
ns
tRECRSTB
RESET Recovery
6.58
ns
tMPWRSTB
RESET Minimum Pulse Width
1.18
ns
tCYC
Clock Cycle Time
10.90
ns
FMAX
Maximum Frequency
92
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
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