2-66 Revision 13 I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and
參數(shù)資料
型號(hào): AGLE600V5-FG484I
廠商: Microsemi SoC
文件頁數(shù): 146/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 600K 484-FBGA
標(biāo)準(zhǔn)包裝: 60
系列: IGLOOe
邏輯元件/單元數(shù): 13824
RAM 位總計(jì): 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
IGLOOe DC and Switching Characteristics
2-66
Revision 13
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Figure 2-26 Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
TRIBUF
CLKBUF
INBUF
CLKBUF
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
Pad
Out
CLK
Enable
Preset
Data_out
Data
EOUT
DOUT
Enable
CLK
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
D_Enable
A
B
C
D
E
F
G
H
I
J
L
K
Y
Core
Array
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