Revision 16 2-55 Timing Characteristics 1.5 V DC Core Voltage Figure 2-20 Timing Model and Wavefor" />
參數(shù)資料
型號(hào): AGLP125V2-CSG281I
廠商: Microsemi SoC
文件頁數(shù): 101/134頁
文件大?。?/td> 0K
描述: IC FPGA IGLOO PLUS 125K 281-CSP
標(biāo)準(zhǔn)包裝: 184
系列: IGLOO PLUS
邏輯元件/單元數(shù): 3120
RAM 位總計(jì): 36864
輸入/輸出數(shù): 212
門數(shù): 125000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 281-TFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 281-CSP(10x10)
IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-55
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-20 Timing Model and Waveforms
PRE
CLR
Out
CLK
Data
EN
tSUE
50%
tSUD
tHD
50%
tCLKQ
0
tHE
tRECPRE
tREMPRE
tRECCLR
tREMCLR
tWCLR
tWPRE
tPRE2Q
tCLR2Q
tCKMPWH tCKMPWL
50%
Table 2-82 Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
0.89
ns
tSUD
Data Setup Time for the Core Register
0.81
ns
tHD
Data Hold Time for the Core Register
0.00
ns
tSUE
Enable Setup Time for the Core Register
0.73
ns
tHE
Enable Hold Time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.60
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.62
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.24
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.23
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.30
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.30
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.56
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.56
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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