Revision 16 2-69 Table 2-93 RAM512X18 Commercial-Case Conditions: T
參數(shù)資料
型號: AGLP125V2-CSG281I
廠商: Microsemi SoC
文件頁數(shù): 117/134頁
文件大?。?/td> 0K
描述: IC FPGA IGLOO PLUS 125K 281-CSP
標(biāo)準(zhǔn)包裝: 184
系列: IGLOO PLUS
邏輯元件/單元數(shù): 3120
RAM 位總計: 36864
輸入/輸出數(shù): 212
門數(shù): 125000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 281-TFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 281-CSP(10x10)
IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-69
Table 2-93 RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tAS
Address setup time
0.69
ns
tAH
Address hold time
0.13
ns
tENS
REN, WEN setup time
0.61
ns
tENH
REN, WEN hold time
0.07
ns
tDS
Input data (WD) setup time
0.59
ns
tDH
Input data (WD) hold time
0.30
ns
tCKQ1
Clock High to new data valid on RD (output retained)
3.51
ns
tCKQ2
Clock High to new data valid on RD (pipelined)
1.43
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address –
applicable to opening edge
0.21
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address –
applicable to opening edge
0.25
ns
tRSTBQ
RESET Low to data out Low on RD (flow-through)
1.72
ns
RESET Low to data out Low on RD (pipelined)
1.72
ns
tREMRSTB
RESET removal
0.51
ns
tRECRSTB
RESET recovery
2.68
ns
tMPWRSTB RESET minimum pulse width
0.68
ns
tCYC
Clock cycle time
6.24
ns
FMAX
Maximum frequency
160 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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