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參數(shù)資料
| 型號(hào)： | AGLP125V2-CSG281I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 54/134頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA IGLOO PLUS 125K 281-CSP |
| 標(biāo)準(zhǔn)包裝： | 184 |
| 系列： | IGLOO PLUS |
| 邏輯元件/單元數(shù)： | 3120 |
| RAM 位總計(jì)： | 36864 |
| 輸入/輸出數(shù)： | 212 |
| 門數(shù)： | 125000 |
| 電源電壓： | 1.14 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 281-TFBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 281-CSP（10x10） |
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IGLOO PLUS DC and Switching Characteristics
2-12
Revision 16
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in
the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA
Table 2-18 Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Parameter
Definition
Device-Specific Static Power (mW)
AGLP125
AGLP060
AGLP030
PDC1
Array static power in Active mode
PDC2
Array static power in Static (Idle) mode
PDC3
Array static power in Flash*Freeze mode
PDC4
Static PLL contribution
0.901
PDC5
Bank quiescent power (VCCI-dependent)
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet
calculator or the SmartPower tool in Libero SoC software.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLP125-V2CSG289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V2-CSG289 | 功能描述:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| AGLP125-V2CSG289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125-V2CSG289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V2-CSG289I | 功能描述:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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