參數(shù)資料
型號(hào)： AK7716VT
英文描述： Consumer IC
中文描述： 消費(fèi)性IC
文件頁(yè)數(shù)： 27/60頁(yè)
文件大小： 1171K
代理商： AK7716VT
[ASAHI KASEI]
[AK7716]
<M0057-E-01>
1999/09
- 27 -
2-1) CONT0 : clock and interface selector
This register is enable only at system reset state ( DSP_RESET =”L”, CODEC_RESET =”L”)
Command Code
Write
Read
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
60h
70h
CONT0
CKS1
CKS0
DIF
DIF1
DIF0
DISCK
SELCKO
X
00h
D7,D6: Master clock selector
Mode
1
2
3
4
D7
0
0
1
1
D6
0
1
0
1
512fs
384fs
TEST mode (Don’t use).
256fs
D5:DIF Audio interface selector
0:AKM method
1: I2S compatible ( In this case, all input / output pins are I2S compatible.)
D4,D3:DIF1,DIF0 SDIN1,SDIN2 Input mode selector
Mode
1
2
3
4
Note) When D5= 1, the state is I2S compatible independently of mode setting, however set to Mode 1.
D4
0
0
1
1
D3
0
1
0
1
MSB justified (24bit)
LSB justified (24bit)
LSB justified (20bit)
LSB justified (16bit)
D2:DISCK LRCLK,BITCLKOutput control
0: Normal Operation
1: This setting can fix BITCLK=”L” and LRCLK=”H” at master mode.
(Note In case of I2S compatible setting, it become LRCLK=”L”.)
This setting is available only for use the AK7716 analog input and analog output.
D1:SELCKO CLKO Output selector.
0:CLKO outputs the same frequency as XTI.
1:CLKO outputs 1/2 frequency of XTI.
Note) In the case of select 1, after setting CONT0 (when the last clock of SCLK rise up) CLKO will change its frequency.
So, the click noise comes out at this change.
Until INIT_RESET changes to ”L” or changes control register, the output frequency does not change.
Phase matching between CLKO and XTI is done at INIT_RESET =”L”.
D0: Always 0
Note) Underlines of the setting of
~
mean default setting.
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