參數(shù)資料
型號(hào)： AK7716VT
英文描述： Consumer IC
中文描述： 消費(fèi)性IC
文件頁(yè)數(shù)： 41/60頁(yè)
文件大?。?/td> 1171K
代理商： AK7716VT
[ASAHI KASEI]
[AK7716]
<M0057-E-01>
1999/09
- 41 -
7-1-e) External conditional jump code write (during reset phase)
The data comprising a set of two bytes is used to perform an external conditional jump code write operation. The data can be inputed during
both the reset and operation phases, and the input data are set to the specified register at the leading edge of the LRCLK. When all data bits
have been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump command will be executed if
there is any one agreement between "1" of each bit of external condition code 8 bits (soft set) plus 1 bit (hard set) at the external input
terminal JX and "1" of each bit of the IFCON field. The data during the reset phase can be written only before release of the reset, after all
data has been transferred. RQ Transition from "L" to "H" in the write operation during the reset phase must be execured after three
LRCLK in the slave mode, one LRCLK in master mode, respectively, from the trailing edge of the LRCLK after release of the reset. Then
the RDY goes to "H" after capturing the rise of the next LRCLK. A write operation from the microcomputer is disabled until the RDY goes
to "H". The IFCON field provides external conditions written on the program.
Note: It should be noted that the LRCLK phase is inverted in the I2S-compatible state.
7
0 JX
External condition code
nnnnnnnno
á
Check if there is any one agreement between the bit specified
in IFCON and "1" in the external condition code
16
a
8
IFCON field
uuuuuuuu
Data transfer procedure
Command code C4h ( 1 1 0 0 0 1 0 0)
Code data (D7 . . . . . D0)
Timing for external conditional jump write operation (during reset phase)
RDY
RESET
11000100 D7 . . . D0
SI
SO
SCLK
RQ
2LRCLK(max)
LRCLK
L ch R ch
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