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參數(shù)資料
| 型號： | Alert on LAN ASIC |
| 廠商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系統(tǒng)監(jiān)控指示設備) |
| 中文描述： | 系統(tǒng)監(jiān)測儀器設備（系統(tǒng)監(jiān)控指示設備） |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
11
Networking Silicon — Alert on LAN* ASIC
2.6
Synchronous RAM and Packet Control
There is a 128-byte synchronous RAM block inside of the Alert on LAN ASIC primarily used for
storing the packet to be sent. The contents of the EEPROM are directly loaded into RAM when an
EEPROM load occurs. The packet control block is responsible for adding TCO data and dynamic
packet data to the RAM and controlling the TCO block to send each packet out to the TCO
interface.
2.7
Clock Synchronization Logic
The clock synchronization logic is used to provide a smooth transition of clocks for the 82558B.
Since the 82558B requires a clock for TCO support in low power states, clock synchronization
logic is a necessity. This logic ensures that the transition between the PCI clock and the 25 MHz
clock generated by the 82558B is smooth and non-glitching. This assures that the 82558B
continues to operate in a known state.
PCI_CK and B25_CK are the PCI and the 82558B 25 MHz output clocks, respectively. The Alert
on LAN ASIC must monitor both in order to provide a smooth transition between both clocks.
Both clocks are required during the power state transition (in other words, PWR_GOOD transitions
low). after the Main Power Good signal transitions low at least 3 PCI clocks are required to switch
from the PCI clock to the 82558B’s 25 MHz clock.
PCI_SEL and B25_SEL are the PCI and the 82558B 25 MHz clock gates, respectively. These
outputs control analog switches that can turn the clocks on or off.
Note:
The analog switches used must be selected carefully to guarantee that the PCI clock skew
specifications are not violated.
2.8
SMI Logic
The SMI# signal is asserted (active low) if the Event Status and the SMI Mask bits are set for any
particular event, with the exception of a software event. The software event cannot be used to
generate an SMI.
Since the SMI# requires both the Event Status and the SMI mask for one event to be set, clearing
any one of these two bits will de-assert the SMI# signal if it is the only event causing the SMI#.
If one external event has occurred and the SMI mask bit is set, the SMI# signal will be active. If the
event is cleared by writing a 1b to the appropriate status bit, the event will be cleared in the Alert on
LAN ASIC. However, if the event is still active, it will be set again in the Event Status register. The
net result is that the SMI# line will pulse inactive for a single 25 MHz clock cycle. If this is
undesired, software will need to take steps to avoid this. This can be achieved by disabling the SMI
mask bit or ensuring that the external event is no longer active.
SMI events can happen independently or jointly with packet transmission events since each has its
own SMI Mask register.
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