參數(shù)資料
型號(hào): Alert on LAN ASIC
廠商: Intel Corp.
英文描述: System Monitoring Instrumentation Device(系統(tǒng)監(jiān)控指示設(shè)備)
中文描述: 系統(tǒng)監(jiān)測(cè)儀器設(shè)備(系統(tǒng)監(jiān)控指示設(shè)備)
文件頁(yè)數(shù): 30/36頁(yè)
文件大?。?/td> 231K
代理商: ALERT ON LAN ASIC
Alert on LAN* ASIC — Networking Silicon
26
Datasheet
5.3
Vector Test Mode
The Alert on LAN ASIC can be put into two different test modes for allowing easier access to
registers during testing. By setting TST_MODE in the Test Mode register, the Alert on LAN ASIC
provides a special parallel data interface for easy input and output. The ASIC can also be put into a
“fast” mode that internally configures the Alert on LAN ASIC such that counters and state
machines are free running. This is done by setting the TST_FAST bit in the Test Mode register.
These Vector Test Modes are used to provide a method of obtaining better and faster test coverage
of internal nodes, helping facilitate higher yields and achieve higher probability of error-free
devices on the ASIC manufacturing line. These modes are not recommended in normal operation
of Alert on LAN ASIC.
Note:
The Vector Test Mode mode will make the Alert on LAN ASIC unusable in its intended operation.
These are special modes that are only intended for more efficient test vector coverage.
5.3.1
Vector Input Interface
The input interface to the Vector Test Mode uses 9 bits: 8 bits for data and 1 bit to select between an
address phase and a data phase. There is no chip select, which means that an address phase or a
data phase will occur at every rising edge of the Alert on LAN ASIC clock.
The 8-bit address/data signals used are TREADY#, EVENT_6, EVENT_5, EVENT_4, EVENT_3,
EVENT_2, EVENT_1, and TSTATUS#. The order listed shows the bit order with TREADY# as
the most significant bit and TSTATUS# as the least significant bit.
The address/data select input is the TACTIVE signal. When it equals 0b, an address phase occurs
on the next rising edge; when the signal is a 1b, a data phase occurs.
The addressing scheme for the input interface is described in
Table 1
.
Note:
This is only an input interface.
Section 5.3.2, “Vector Output Interface”
describes the output
interface in more detail.
5.3.2
Vector Output Interface
The output interface in Vector Test Mode uses 8 bits. This output bus is simply a result of the
current addresses latched from the vector input interface. For example, if the last address phase on
the input vector interface was 10001001b, some propagation delay after this value is latched in on
the rising clock edge, the output interface would show the results of the RAM, address 09h.
The 8-bit data output signals used are TDATA[7:0]. This order shows the bit order, where TDATA7
is the most significant bit and TDATA0 is the least significant bit.
Table 1. Vector Input Interface Addressing Scheme
Data Select
(TACTIVE)
AD[7:0]
Description
0
1RRRRRRR
This is the address phase where “RRRRRRR” addresses RAM.
This allows addressing to all 128 bytes of RAM.
0
0XXRRRRR
This is the address phase where “RRRRR” addresses the Alert on
LAN ASIC registers. This addresses up to 32 registers. “XX” are
“don’t care” bits.
1
DDDDDDDD
This is the data phase where “DDDDDDDD” is the data that is
written to the previously latched address from an address phase.
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