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參數(shù)資料
| 型號： | Alert on LAN ASIC |
| 廠商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系統(tǒng)監(jiān)控指示設備) |
| 中文描述： | 系統(tǒng)監(jiān)測儀器設備（系統(tǒng)監(jiān)控指示設備） |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
15
Networking Silicon — Alert on LAN* ASIC
3.5
EEPROM Interface Signals
3.6
Alert/SOS Events Signals
3.7
Miscellaneous Signals
Symbol
Pin
Type
Name and Function
EE_CS
18
O, 1 mA
EEPROM Chip Select.
EEPROM Chip Select is used to control
access to the EEPROM.
EE_SK
19
O, 1 mA
EEPROM Shift Clock.
The EE_SK signal is used to shift data in and
out of the EEPROM.
EE_DO
21
I, TTL,
PU
EEPROM Data Out.
Serial data output from the EEPROM.
EE_DI
20
O, 1 mA
EEPROM Data In.
Serial data input to the EEPROM.
Symbol
Pin
Type
Name and Function
EVENT_1
22
I/O, TTL,
S, 4 mA
Event_1 - Cover Tamper.
Level input that causes alert 1 packet
transmission. This pin can be used as output as a clearing mechanism
on external sticky logic.
EVENT_2
23
I, TTL, S
Event_2 - ENV_SMI.
Level input that causes alert 2 packet
transmission.
EVENT_3
24
I, TTL, S
Event_3 - BTI_Temperature.
Level input that causes alert 3 packet
transmission.
EVENT_4
25
I, TTL, S
Event_4 - LANLeash.
Level input that causes alert 4 packet
transmission.
EVENT_5
26
I, TTL, S
Event_5 - Processor Missing.
Level input that causes alert 5 packet
transmission.
Reserved
29
N/A
This pin is reserved and should be pulled down to 0b via a 220
resistor.
Symbol
Pin
Type
Name and Function
PCI_RST#
32
I, TTL
PCI Reset.
The PCI_RST# pin is an active low input signal from the
PCI interface. It propagates to the 82558B through the 82558_RST#
line if PWR_GOOD is active. It is also used as an indication to the
Alert on LAN ASIC that the 82558B is being reset.
82558_RST#
15
O, 2 mA
82558 Reset.
The 82558 Reset signal is an active low reset. It is
driven when the PCI_RST# signal is active and the PWR_GOOD
signal is active. It is also driven when an 82558B software reset is
triggered through the internal registers.
ISOLATE#
33
O, 2 mA
Isolate Output.
This output signal is used to isolate the PCI bus on
the 82558B. It implements the 82558B Wake on LAN* (WOL) circuitry
to guarantee that the ALTRST# signal of the 82558B is asserted
before ISOLATE# is asserted. This is based on the PWR_GOOD and
AUX_GOOD signals.
SMI#
34
O, OD,
2 mA
SMI Output.
The SMI# signal is asserted by the Alert on LAN ASIC
for various events depending on the SMI mask register settings. SMI#
is de-asserted by clearing the events or masks in the Alert on LAN
ASIC's status registers.
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