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參數(shù)資料
| 型號： | AM29DL642G90MDI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| 中文描述： | 8M X 16 FLASH 3.3V PROM MODULE, 90 ns, PBGA63 |
| 封裝： | 10.95 X 11.95 MM, 0.80 MM PITCH, FBGA-63 |
| 文件頁數(shù)： | 32/54頁 |
| 文件大小： | 828K |
| 代理商： | AM29DL642G90MDI |
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30
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
Table 13.
Am29DL642G Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector. Refer to
Table 2 for information on sector addresses.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased. A21–A19 uniquely select a bank.
Notes:
1.
2.
3.
See Table 1 for description of bus operations.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
Unless otherwise noted, address bits A21–A11 are don’t cares for
unlock and command cycles, unless SA or PA is required.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence
section for more information.
4.
5.
6.
7.
8.
9.
The device ID must be read across the fourth, fifth, and sixth
cycles.
10. The data is 80h for factory locked and 00h for not factory locked.
11. The data is 00h for an unprotected sector/sector block and 01h for
a protected sector/sector block.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the
read mode when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command
Sequence
(Note 1)
C
Bus Cycles (Notes 2–5)
Third
Addr
Data
First
Second
Addr
Fourth
Addr
Fifth
Sixth
Addr
RA
XXX
555
555
Data
RD
F0
AA
AA
Data
Data
Addr
Data
Addr
Data
Read (Note 6)
Reset (Note 7)
A
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Unlock Bypass
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
Chip Erase
Sector Erase
Erase Suspend (Note 14)
Erase Resume (Note 15)
CFI Query (Note 16)
1
1
4
6
Manufacturer ID
Device ID (Note 9)
SecSi Sector Factory Protect
(Note 10)
2AA
2AA
55
55
(BA)555
(BA)555
90
90
(BA)X00
(BA)X01
01
7E
(BA)X0E
02
(BA)X0F
01
4
555
AA
2AA
55
(BA)555
90
(BA)X03 80/00
Sector/Sector Block Protect
Verify (Note 11)
4
555
AA
2AA
55
(BA)555
90
(SA)X02 00/01
3
4
4
3
2
2
6
6
1
1
1
555
555
555
555
XXX
BA
555
555
BA
BA
55
AA
AA
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
PA
XXX
2AA
2AA
55
55
55
55
PD
00
55
55
555
555
555
555
88
90
A0
20
XXX
PA
00
PD
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
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