參數(shù)資料
型號(hào): Am29F016B-70FIB
廠商: Advanced Micro Devices, Inc.
英文描述: CAP 82PF 100V 2% NP0(C0G) SMD-0603 TR-7 PLATED-NI/SN
中文描述: 16兆位(2米× 8位)的CMOS 5.0伏只,統(tǒng)一部門快閃記憶體
文件頁數(shù): 12/38頁
文件大?。?/td> 477K
代理商: AM29F016B-70FIB
12
Am29F016B
P R E L I M I N A R Y
Figure 1.
Temporary Sector Group Unprotect
Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary
Sector Group Unprotect
Completed (Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
21444B-8
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