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參數(shù)資料
| 型號： | AM29PDLI27H63PCI |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位），3.0伏的CMOS只，頁面模式同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶 |
| 文件頁數(shù)： | 57/68頁 |
| 文件大?。?/td> | 750K |
| 代理商： | AM29PDLI27H63PCI |
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June 30, 2003
Am29PDL127H
55
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
OE#
CE#
WE#
Addresses
t
OH
Data
Valid
In
Valid
In
Valid PA
Valid RA
t
WC
t
WPH
t
AH
t
WP
t
DS
t
DH
t
AS
t
RC
t
CE
t
AH
Valid
Out
t
OE
t
ACC
t
OEH
t
GHWL
t
DF
Valid
In
CE# Controlled Write Cycles
WE# Controlled Write Cycle
Valid PA
Valid PA
t
CP
t
CPH
t
WC
t
WC
Read Cycle
t
SR/W
t
AS
Figure 18.
Back-to-back Read/Write Cycle Timings
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ6–DQ0
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle.
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
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