
SPRS550C
– OCTOBER 2009 – REVISED MARCH 2011
6.6.11 I
2C Interface
The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus.
The I2C controller supports the multimaster mode which allows more than one device capable of
controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can
operate as either transmitter or receiver, according to the function of the device. In addition to being a
transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when
performing data transfers. This data transfer is carried out via two serial bidirectional wires:
An SDA data line
An SCL clock line
The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing
format. The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode
(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .
6.6.11.1 I2C Standard/Fast-Speed Mode
Table 6-126. I2C Standard/Fast-Speed Mode Timings
1.8V, 3.3-V
NO.
PARAMETER(1)
STANDARD
FAST MODE
UNIT
MODE
MIN
MAX
MIN
MAX
fSCL
Clock Frequency, i2cX_scl
100
400
kHz
I1
tw(SCLH)
Pulse Duration, i2cX_scl high
4
0.6
s
I2
tw(SCLL)
Pulse Duration, i2cX_scl low
4.7
1.3
s
I3
tsu(SDAV-SCLH)
Setup time, i2cX_sda valid before i2cX_scl active level
250
100(2)
ns
I4
th(SCLHSDAV)
Hold time, i2cX_sda valid after i2cX_scl active level
3.45(3)
0.9(3)
s
I5
tsu(SDAL-SCLH)
Setup time, i2cX_scl high after i2cX_sda low (for a
4.7
0.6
s
START(4) condition or a repeated START condition)
I6
th(SCLHSDAH)
Hold time, i2cX_sda low level after i2cX_scl high level
4
0.6
s
(STOP condition)
I7
th(SCLHRSTART)
Hold time, i2cX_sda low level after i2cX_scl high level (for
4
0.6
s
a repeated START condition)
I8
tw(SDAH)
Pulse duration, i2cX_sda high between STOP and START
4.7
1.3
s
conditions
tR(SCL)
Rise time, i2cX_scl
1000
300
ns
tF(SCL)
Fall time, i2cX_scl
300
ns
tR(SDA)
Rise time, i2cX_sda
1000
300
ns
tF(SDA)
Fall time, i2cX_sda
300
ns
CB
Capacitive load for each bus line
60
pF
(1)
In i2cX, X is equal to 1, 2, or 3.
(2)
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) 250 ns must then be
met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low
period of the i2cx_scl, it must output the next data bit to the i2cx_sda line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according
to the standard-mode I2C-bus specification) before the i2cx_scl line is released.
(3)
The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl signal.
(4)
After this time, the first clock is generated.
Copyright
2009–2011, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
193