SPRS550C
– OCTOBER 2009 – REVISED MARCH 2011
Table 2-3. Multiplexing Characteristics (continued)
ZER
ZCN
MODE 0
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
C10
P22
mcbsp1_dx
mcspi4_simo
mcbsp3_dx
gpio_158
safe_mode
C9
P23
mcbsp1_dr
mcspi4_somi
mcbsp3_dr
gpio_159
safe_mode
E11
P25
mcbsp_clks
gpio_160
uart1_cts
safe_mode
C11
P24
mcbsp1_fsx
mcspi4_cs0
mcbsp3_fsx
gpio_161
safe_mode
C8
N24
mcbsp1_clkx
mcbsp3_clkx
gpio_162
safe_mode
W15
N2
uart3_cts_rctx
gpio_163
safe_mode
W13
N3
uart3_rts_sd
gpio_164
safe_mode
AA13
P1
uart3_rx_irrx
gpio_165
safe_mode
Y13
P2
uart3_tx_irtx
gpio_166
A6
F25
usb0_dp
(1)
uart3_tx_irtx
B6
F24
usb0_dm
(1)
uart3_rx_irrx
C7
G24
usb0_vbus
B7
G25
usb0_id
A7
E25
usb0_drvvbus
uart3_tx_irtx
gpio_125
safe_mode
AB15
V2
hecc1_txd
uart3_rx_irrx
gpio_130
safe_mode
AB16
V3
hecc1_rxd
uart3_rts_sd
gpio_131
safe_mode
AA17
V4
i2c1_scl
AB17
V5
i2c1_sda
Y17
W1
i2c2_scl
gpio_168
safe_mode
Y16
W2
i2c2_sda
gpio_183
safe_mode
W16
W4
i2c3_scl
gpio_184
safe_mode
W17
W5
i2c3_sda
gpio_185
safe_mode
B9
L25
hdq_sio
sys_altclk
i2c2_sccbe
i2c3_sccbe
gpio_170
safe_mode
K22
AE14
mcspi1_clk
mmc2_dat4
gpio_171
safe_mode
K19
AD15
mcspi1_simo
mmc2_dat5
gpio_172
safe_mode
J18
AC15
mcspi1_somi
mmc2_dat6
gpio_173
safe_mode
K18
AB15
mcspi1_cs0
mmc2_dat7
gpio_174
safe_mode
J20
AD14
mcspi1_cs1
mmc3_cmd
gpio_175
safe_mode
J19
AE15
mcspi1_cs2
mmc3_clk
gpio_176
safe_mode
J21
AE16
mcspi1_cs3
hsusb2_data2
gpio_177
mm_fsusb2_txdat
safe_mode
J22
AD16
mcspi2_clk
hsusb2_data7
gpio_178
safe_mode
H20
AC16
mcspi2_simo
gpt9_pwm_evt
hsusb2_data4
gpio_179
safe_mode
H22
AB16
mcspi2_somi
gpt10_pwm_evt
hsusb2_data5
gpio_180
safe_mode
H21
AA16
mcspi2_cs0
gpt11_pwm_evt
hsusb2_data6
gpio_181
safe_mode
H19
AE17
mcspi2_cs1
gpt8_pwm_evt
hsusb2_data3
gpio_182
mm_fsusb2_txen
safe_mode
_n
AB18
Y1
sys_nirq
gpio_0
safe_mode
E10
M25
sys_clkout2
gpio_186
safe_mode
G22
AD17
etk_clk
mcbsp5_clkx
mmc3_clk
hsusb1_stp
gpio_12
hw_dbg0
G21
AE18
etk_ctl
mmc3_cmd
hsusb1_clk
gpio_13
mm_fsusb1_rxdp
hw_dbg1
G20
AD18
etk_d0
mcspi3_simo
mmc3_dat4
hsusb1_data0
gpio_14
mm_fsusb1_rxrcv
hw_dbg2
F22
AC18
etk_d1
mcspi3_somi
hsusb1_data1
gpio_15
mm_fsusb1_txse
hw_dbg3
0
F20
AB18
etk_d2
mcspi3_cs0
hsusb1_data2
gpio_16
mm_fsusb1_txdat
hw_dbg4
G19
AA18
etk_d3
mcspi3_clk
mmc3_dat3
hsusb1_data7
gpio_17
hw_dbg5
E19
Y18
etk_d4
mcbsp5_dr
mmc3_dat0
hsusb1_data4
gpio_18
hw_dbg6
F21
AE19
etk_d5
mcbsp5_fsx
mmc3_dat1
hsusb1_data5
gpio_19
hw_dbg7
F19
AD19
etk_d6
mcbsp5_dx
mmc3_dat2
hsusb1_data6
gpio_20
hw_dbg8
E21
AB19
etk_d7
mcspi3_cs1
mmc3_dat7
hsusb1_data3
gpio_21
mm_fsusb1_txen
hw_dbg9
_n
D22
AE20
etk_d8
mmc3_dat6
hsusb1_dir
gpio_22
hw_dbg10
D21
AD20
etk_d9
mmc3_dat5
hsusb1_nxt
gpio_23
mm_fsusb1_rxdm
hw_dbg11
E22
AC20
etk_d10
uart1_rx
hsusb2_clk
gpio_24
hw_dbg12
E20
AB20
etk_d11
mcspi3_clk
hsusb2_stp
gpio_25
mm_fsusb2_rxdp
hw_dbg13
E18
AE21
etk_d12
hsusb2_dir
gpio_26
hw_dbg14
D20
AD21
etk_d13
hsusb2_nxt
gpio_27
mm_fsusb2_rxdm
hw_dbg15
(1)
This mux selection is controlled by CONTROL_DEVCONF2 register.
Copyright
2009–2011, Texas Instruments Incorporated
TERMINAL DESCRIPTION
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