參數(shù)資料
型號(hào): AM41DL6408H8H85IT
廠商: Advanced Micro Devices, Inc.
元件分類(lèi): SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁(yè)數(shù): 56/66頁(yè)
文件大?。?/td> 1123K
代理商: AM41DL6408H8H85IT
54
Am41DL6408H
November 24, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
SRAM Read Cycle
Note:
CE1#s = OE# = V
IL
, CE2s = WE# = V
IH
, UB#s and/or LB#s = V
IL
Figure 29.
SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
Speed
Unit
71
70
85
t
RC
Read Cycle Time
Min
55
70
85
ns
t
AA
Address Access Time
Max
55
70
85
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
55
70
85
ns
t
OE
Output Enable Access Time
Max
25
35
45
ns
t
BA
LB#s, UB#s to Access Time
Max
55
70
85
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
Min
10
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
10
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip Disable to High-Z Output
Max
20
25
ns
t
BHZ
UB#s, LB#s Disable to High-Z Output
Max
20
25
ns
t
OHZ
Output Disable to High-Z Output
Max
20
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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