參數(shù)資料
型號: AM41DL6408H8H85IT
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 62/66頁
文件大?。?/td> 1123K
代理商: AM41DL6408H8H85IT
60
Am41DL6408H
November 24, 2003
A D V A N C E I N F O R M A T I O N
SRAM DATA RETENTION
Notes:
1. CE1#s
V
CC
– 0.2 V CE2s
V
CC
– 0.2 V (CE1#s controlled) or CE2s
0.2 V (CE2s controlled), CIOs = V
SS
or V
CC
.
2. Typical values are not 100% tested.
Figure 34.
CE1#s Controlled Data Retention Mode
Figure 35.
CE2s Controlled Data Retention Mode
Parameter
Symbol
Parameter Description
Test Setup
Min
Typ
Max
Unit
V
DR
V
CC
for Data Retention
CS1#s
V
CC
– 0.2 V (Note 1)
V
CC
= 3.0 V, CE1#s
V
CC
– 0.2 V
(Note 1)
1.5
3.3
V
I
DR
Data Retention Current
1.0
(Note 2)
15
μA
t
SDR
t
RDR
Data Retention Set-Up Time
See data retention waveforms
0
ns
Recovery Time
t
RC
ns
V
DR
V
CC
2.7V
2.2V
CE1#s
GND
Data Retention Mode
CE1#s
V
CC
-
0.2 V
t
SDR
t
RDR
V
CC
2.7 V
CE2s
0.4 V
GND
V
DR
Data Retention Mode
t
SDR
t
RDR
CE2s <
0.2 V
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