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參數(shù)資料
| 型號： | AM45DL32X8G |
| 英文描述： | 200NS, FLATPACK, 883C; LEV B COMPLIANT(EEPROM) |
| 中文描述： | Am45DL32x8G -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 60/64頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | AM45DL32X8G |
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August 28, 2002
Am45DL32x8G
59
P R E L I M I N A R Y
CompactCell SRAM AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 32.
CompactCell SRAM Write Cycle
—
UB#s and LB#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out
High-Z
High-Z
t
WC
CE1#s
CE2s
t
AW
t
BW
t
DW
t
DH
t
WR
(See Note 3)
t
AS
(See Note 4)
t
CW
(See Note 2)
t
CW
(See Note 2)
t
WP
(See Note 5)
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