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參數(shù)資料
| 型號： | AM486DXSQFP |
| 英文描述： | 70NS, PLCC, IND TEMP(EEPROM) |
| 中文描述： | Am486DX采用SQFP - Am486DX采用SQFP包溫度比較 |
| 文件頁數(shù)： | 28/52頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | AM486DXSQFP |
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28
Am486DE2 Microprocessor
The following is a summary of the key features in the
SMM environment:
I
Real mode style address calculation
I
4-Gbyte limit checking
I
IF flag is cleared
I
NMI is disabled
I
TF flag in EFLAGS is cleared; single step traps are
disabled
I
DR7 is cleared; debug traps are disabled
I
The RSM instruction no longer generates an invalid
op code error
I
Default 16-bit op code, register, and stack use
I
All bus arbitration (HOLD, AHOLD, BOFF) inputs
and bus sizing (BS8, BS16) inputs operate normally
while the CPU is in SMM.
Executing System Management Mode
Handler
The processor begins execution of the SMI handler at
offset 8000h in the CS segment. The CS Base is initially
30000h, as shown in Table 5.
The CS Base can be changed using the SMM Base
relocation feature. When the SMI handler is invoked, the
CPU’s PE and PG bits in CR0 are reset to 0. The pro-
cessor is in an environment similar to Real mode, but
without the 64-Kbyte limit checking. However, the de-
fault operand size and the default address size are set
to 16 bits. The EM bit is cleared so that no exceptions
are generated. (If the SMM was entered from Protected
mode, the Real mode interrupt and exception support is
not available.) The SMI handler should not use floating-
point unit instructions until the FPU is properly detected
(within the SMI handler) and the exception support is
initialized.
Because the segment bases (other than CS) are cleared
to 0 and the segment limits are set to 4 Gbyte, the ad-
dress space may be treated as a single, flat 4-Gbyte
linear space that is unsegmented. The CPU is still in
Real mode and when a segment selector is loaded with
a 16-bit value, that value is then shifted left by 4 bits and
loaded into the segment base cache.
In SMM, the CPU can access or jump anywhere within
the 4-Gbyte logical address space. The CPU can also
indirectly access or perform a near jump anywhere with-
in the 4-Gbyte logical address space.
Exceptions and Interrupts with System
Management Mode
When the CPU enters SMM, it disables INTR interrupts,
debug, and single-step traps by clearing the EFLAGS,
DR6, and DR7 registers. This prevents a debug appli-
cation from accidentally breaking into an SMI handler.
Table 4. SMM Initial CPU Core Register Settings
Register
SMM Initial State
General
Purpose
Registers
Unmodified
EFLAGS
0000 0002h
CR0
Bits 0, 2, 3, and 31 cleared (PE, EM, TS,
and PG); remainder unmodified
DR6
Unpredictable state
DR7
0000 0400h
GDTR, LDTR,
IDTR, TSSR
Unmodified
EIP
Note:
Interrupts from INT and NMI are disabled on SMM
entry.
0000 8000h
Table 5. Segment Register Initial States
Segment
Register
Selector
Base
Attributes
Limit
1
CS
2
3000h
30000h
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
4 Gbyte
DS
0000h
00000000h
4 Gbyte
ES
0000h
00000000h
4 Gbyte
FS
0000h
00000000h
4 Gbyte
GS
0000h
00000000h
4 Gbyte
SS
0000h
00000000h
4 Gbyte
1. The segment limit check is 4 Gbyte instead of the usual
64K.
2. The Selector value for CS remains at 3000h even if the
SMBASE is changed.
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