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參數(shù)資料
| 型號： | AM486DXSQFP |
| 英文描述： | 70NS, PLCC, IND TEMP(EEPROM) |
| 中文描述： | Am486DX采用SQFP - Am486DX采用SQFP包溫度比較 |
| 文件頁數(shù)： | 37/52頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | AM486DXSQFP |
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Am486DE2 Microprocessor
37
Am486DE2 MICROPROCESSOR FUNCTIONAL DIFFERENCES
The Am486DE2 microprocessor is a new member of the
AMD Am486 family, which also includes the Enhanced
Am486 and the Am486DX microprocessors.
Although the Am486DE2 is based on and compatible
with the Enhanced Am486 microprocessors, it has no
support for write-back cache.
Several important differences exist between the
Am486DE2 and the Am486DX processors:
I
The Am486DE2 ID register contains a different
version signature than the Am486DX. It has the
same ID register as the Enhanced Am486DX2 in
Write-through mode.
I
A burst write feature is available for copy-backs. The
FLUSH pin and WBINVD instruction copy-back all
modified data to external memory prior to issuing the
special bus cycle or reset.
I
The RESET state is invoked either after power up or
after the RESET signal is applied according to the
standard Am486DX microprocessor specification.
I
After reset, the STATUS bits of all lines are set to 0.
The LRU bits of each set are placed in a starting
state.
In addition, the differences in the processors are high-
lighted in Table 12.
Am486DE2 MICROPROCESSOR IDENTIFICATION
The Am486DE2 microprocessor supports two standard
methods for identifying the CPU in a system. The report-
ed values are dynamically assigned based on the CPU
type and the status of the WB/WT pin input at RESET.
DX Register at RESET
The DX register always contains a component identifier
at the conclusion of RESET. The upper byte of DX (DH)
contains 04 and the lower byte of DX (DL) contains a
CPU type/stepping identifier (see Table 13).
CPUID Instruction
The Am486DE2 implements a new instruction that
makes information available to software about the
family, model, and stepping of the microprocessor on
which it is executing. Support of this instruction is
indicated by the presence of a user-modifiable bit in
position EFLAGS.21, referred to as the EFLAGS.ID bit.
This bit is reset to zero at device reset (RESET or
SRESET) for compatibility with existing processor
designs.
CPUID Timing
CPUID execution timing depends on the selected EAX
parameter values (see Table 14).
Table 12. Am486DE2 Microprocessor Functional Differences
Processor
Cache
Clock
Major
Enhancements
Package
Am486DX2-66
8 Kbyte,
Write-through
1x, 2x
168-Pin PGA
Enhanced
Am486DX2-66
8-Kbyte,
Write-through/
Write-back
2x, 3x
SMI, write-back
168-Pin PGA
Am486DE2-66
8-Kbyte,
Write-through
2x
SMI
168-Pin PGA,
208-Lead SQFP
Table 13. CPU ID Codes
CPU Type and Cache Mode
Component
ID (DH)
Revision
ID (DL)
DE2 in Write-through mode
04
3x
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM486 | Am486 Microprocessor Software User＇s Manual? 4.40MB (PDF) |
| AM49DL3208G | Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM |
| AM49DL320BG | Am49DL320BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM49DL32XBG | Am49DL32xBG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM49DL640BH | Am49DL640BH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM486-EVAL-KIT | 制造商:Advanced Micro Devices 功能描述:AM486CDP EVAL KIT |
| AM4874N | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 30-V (D-S) MOSFET |
| AM4890N | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:Dual N-Channel 150-V (D-S) MOSFET |
| AM4892N | 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:Dual N-Channel 150-V (D-S) MOSFET |
| AM48S-12-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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