參數(shù)資料
型號: AM49DL3208GB70FS
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA69
封裝: 8 X 10 MM, FBGA-69
文件頁數(shù): 22/61頁
文件大小: 904K
代理商: AM49DL3208GB70FS
March 12, 2004
Am49DL3208G
27
ADV ANCE
I N FO RMAT I O N
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
Refer to the Flash Write Operation Status section for
information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity. Note that
the SecSi Sector, autoselect, and CFI functions are
unavailable when an erase operation in is progress.
Figure 5 illustrates the algorithm for the erase opera-
tions tables in the AC Characteristics section for
parameters, and Figure 20 section for timing dia-
grams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 80 s time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 s to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation. Addresses are “don’t-cares” when
writing the Erase suspend command.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Flash Write Operation Status section for
information on these status bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Flash Write Operation Status section for
more information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. The device
allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored
in the memory array. When the device exits the au-
toselect mode, the device reverts to the Erase Sus-
pend mode, and is ready for another valid operation.
tions for details.
To resume the sector erase operation, the system
must write the Erase Resume command (address bits
are don’t care). The bank address of the erase-sus-
pended bank is required when writing this command.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the chip has resumed erasing.
Figure 5.
Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Tables 12 and 13 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
相關(guān)PDF資料
PDF描述
AM4J-67205L-55 8K X 9 OTHER FIFO, 55 ns, CQCC32
AMS1-67205L-35 8K X 9 OTHER FIFO, 35 ns, PQCC32
AM50030C33 SNAP ACTING/LIMIT SWITCH, SPST, MOMENTARY, 0.1A, 30VDC, 2.4mm, PANEL MOUNT
AM51130C43N SNAP ACTING/LIMIT SWITCH, SPST, MOMENTARY, 0.6A, 125VDC, 2.4mm, PANEL MOUNT
AM51164C43N SNAP ACTING/LIMIT SWITCH, SPST, MOMENTARY, 0.6A, 125VDC, 4.6mm, PANEL MOUNT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM49DL320BG 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am49DL320BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM49DL320BGB701 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
AM49DL320BGB701S 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB701T 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB70IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous