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參數(shù)資料
| 型號： | AM49DL3208GB70FS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA69 |
| 封裝： | 8 X 10 MM, FBGA-69 |
| 文件頁數(shù)： | 6/61頁 |
| 文件大?。?/td> | 904K |
| 代理商： | AM49DL3208GB70FS |
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12
Am49DL3208G
March 12, 2004
ADV ANCE
I N FO RMAT I O N
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC +
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5f in the table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS±0.3 V, the device
draws CMOS standby current (I
CC4f). If RESET# is
held at V
IL but not within VSS±0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY (during Embedded Algorithms). The
system can th us monito r RY/BY# to de termin e
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
READY (not during Embedded
Algorithms). The system can read data t
RH after the
RESET# pin returns to V
IH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 17 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2.
Top Boot Sector Addresses
Ba
n
k
Sector
Sector Address
A20–A12
Sector Size
(Kwords)
(x16)
Address Range
Ba
n
k
4
SA0
000000xxx
32
000000h–07FFFh
SA1
000001xxx
32
008000h–0FFFFh
SA2
000010xxx
32
010000h–17FFFh
SA3
000011xxx
32
018000h–01FFFFh
SA4
000100xxx
32
020000h–027FFFh
SA5
000101xxx
32
028000h–02FFFFh
SA6
000110xxx
32
030000h–037FFFh
SA7
000111xxx
32
038000h–03FFFFh
Ba
nk
3
SA8
001000xxx
32
040000h–047FFFh
SA9
001001xxx
32
048000h–04FFFFh
SA10
001010xxx
32
050000h–057FFFh
SA11
001011xxx
32
058000h–05FFFFh
SA12
001100xxx
32
060000h–067FFFh
SA13
001101xxx
32
068000h–06FFFFh
SA14
001110xxx
32
070000h–077FFFh
SA15
001111xxx
32
078000h–07FFFFh
SA16
010000xxx
32
080000h–087FFFh
SA17
010001xxx
32
088000h–08FFFFh
SA18
010010xxx
32
090000h–097FFFh
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