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參數(shù)資料
| 型號(hào)： | AM50DL128CG |
| 英文描述： | 2 x 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 64 Mbit (2 M x 16-Bit) Pseudo Static RAM (Preliminary) |
| 中文描述： | 2 × 64兆位（8米× 8位/ 4米× 16位）的CMOS和64兆位（2米× 16位），偽靜態(tài)存儲(chǔ)器（初步） |
| 文件頁(yè)數(shù)： | 10/70頁(yè) |
| 文件大?。?/td> | 1042K |
| 代理商： | AM50DL128CG |
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May 19, 2003
Am50DL9608G
9
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
Am50DL960
8
G
T
75
I
T
TAPE AND REEL
T
=
S
=
7 inches
13 inches
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85
°
C)
SPEED OPTION
75
=
70
=
70 ns Flash + 55 ns pSRAM
70 ns Flash + 70 ns pSRAM (See page 5)
BOOT SECTOR ARCHITECTURE
T
=
Top Boot of Am29DL320G Flash
B
=
Bottom Boot of Am29DL320G Flash
PROCESS TECHNOLOGY
G
=
0.17 μm
PSEUDO SRAM DEVICE DENSITY
8
=
8 Mbits
AMD DEVICE NUMBER/DESCRIPTION
Am50DL9608G
Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM
Am29DL640G 64 Megabit (8/4 M x 16-Bit) and
Am29DL320G 32 Megabit (4/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
and 8 Mbit (152 K x 16-Bit) Pseudo Static RAM
Valid Combinations
Order Number
Package Marking
Am50DL9608GT70I
Am50DL9608GB70I
T, S
M500000010
M500000011
Am50DL9608GT75I
Am50DL9608GB75I
T, S
M500000012
M500000013
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM50DL128CH | Am50DL128CH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM52-0001 | 1.2 W High Efficiency Power Amplifier 800 - 960 MHz |
| AM52-0001SMB | 1.2 W High Efficiency Power Amplifier 800 - 960 MHz |
| AM52-0001TR | 1.2 W High Efficiency Power Amplifier 800 - 960 MHz |
| AM52-0002 | Industrial Control IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM50DL128CG70IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128CG70IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128CG85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128CG85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128CH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am50DL128CH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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