參數(shù)資料
型號(hào)： AM50DL128CG
英文描述： 2 x 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 64 Mbit (2 M x 16-Bit) Pseudo Static RAM (Preliminary)
中文描述： 2 × 64兆位（8米× 8位/ 4米× 16位）的CMOS和64兆位（2米× 16位），偽靜態(tài)存儲(chǔ)器（初步）
文件頁(yè)數(shù)： 68/70頁(yè)
文件大?。?/td> 1042K
代理商： AM50DL128CG
May 19, 2003
Am50DL9608G
67
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (October 7, 2002)
Initial release.
Revision A+1 (October 14, 2002)
Flash DC Characteristics
Added CMOS compatible table.
Revision A+2 (November 5, 2002)
Distinctive Characteristics
Added Pseudo SRAM access time.
Changed power dissipation standby from 70 μA maxi-
mum to 60 μA.
Changed wording from 1 million write cycles to 1 mil-
lion erase cycles.
Product Selector Guide
Removed the 85 ns speed options.
Added a 75 ns speed option.
Removed a f from CE# Access.
Special Package Handling Instructions
Modified wording.
Ordering Information
Modified order numbers and package markings to re-
flect new speed option.
Pseudo SRAM and Operating Characteristics
Changed the typical and maximum of the Average Op-
erating Current (I
CC1
s and I
CC2
s).
Changed the maximum of the Standby Current
(CMOS) to 70 μA.
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.
Added second bullet, SecSi sector-protect verify text
and figure 3.
SecSi Sector Flash Memory Region, and Enter
SecSi Sector/Exit SecSi Sector Command
Sequence
Added notes, “
Note that the ACC function and unlock
bypass modes are not available when the SecSi sector
is enabled.
”
Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase Com-
mand Sequence
Added “
Note that the SecSi Sector, autoselect, and CFI
functions are unavailable when a [program/erase]
operation is in progress.
”
Common Flash Memory Interface (CFI)
Changed wording in last sentence of third paragraph
from, “...the autoselect mode.” to “...reading array
data.”
Changed CFI website address.
Command Definitions
Changed wording in last sentence of first paragraph
from, “...resets the device to reading array data.” to
...”may place the device to an unknown state. A reset
command is then required to return the device to read-
ing array data.”
Table 12. Am29DL640G Command Definitions
Changed the first address of the unlock bypass reset
command sequence from BA to XXX.
CMOS Compatible
Added I
LR
parameter to table.
Deleted I
ACC
parameter from table.
Changed the maximums of I
CC
3f, I
CC
4f, and I
CC
5f from
5 μA
to 10
μA.
Added Note #6.
Pseudo SRAM DC and Operating Characteristics
Changed the test conditions and maximum for I
SB1
and added the I
SB2
parameter symbol.
Figure 12. Standby Current I
SB
CMOS
Added figure.
Revision A+3 (January 2, 2003)
Pseudo SRAM AC Characteristics
Write Cycle table:
Changed t
DW
to 40 ns.
Physical Dimensions
Deleted A1 specification from table.
Revision A+4 (May 19, 2003)
pSRAM Data Retention, Figure 33. CE#1 Controlled
Data Retention Mode, and Figure 34. CE2s
Controlled Data Retention Mode
Removed table and figures from data sheet.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AM50DL128CG85IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM50DL128CH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am50DL128CH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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